ABSTRACT:

This work presents a novel scheme to schedule loops for
clustered microarchitectures. The scheme is based on a pre-
liminary cluster assignment phase implemented through
graph partitioning techniques followed by a scheduling
phase that integrates register allocation and spill code gen-
eration. The graph partitioning scheme is shown to be very
effective due to its global view of the whole code while the
partition is generated. Results show a significant speedup
when compared with previously proposed techniques. For
some processor configuration the average speedup for the
SPECfp95 is 23% with respect to the published scheme with
the best performance. Besides, the proposed scheme is much
faster (between 2-7 times, depending on the configuration).