This is the only picture I have dressing with a tie (1967)

 

Eduard Ayguadé

 

Full Professor
Computer Architecture Department
Technical University
of Catalunya (UPC)

email: eduard (at) ac (dot) upc (dot) edu

voice: (+34) 93 401 59 51
fax: (+34) 93 401 70 55

Postal address:
  Departament d’Arquitectura de Computadors
  C/ Jordi Girona, 1-3
  Campus Nord, Mod D6 - 210
  E-08034 Barcelona
  Spain

 

Associate Director
Computer Sciences Department
Barcelona Supercomputing Center (BSC-CNS)

email: eduard.ayguade (at) bsc (dot) es

voice: (+34) 93 413 40 37
fax: (+34) 93 413 77 21

Postal address:
  Barcelona Supercomputing Center (BSC-CNS)
  C/ Jordi Girona, 29
  Campus Nord, Edifici Nexus-II
  E-08034 Barcelona
  Spain

CURRICULUM VITAE SUMMARY


Eduard Ayguadé received the Engineering degree in Telecommunications in 1986 and the Ph.D. degree in Computer Science in 1989, both from the Universitat Politècnica de Catalunya (UPC), Spain. Since 1987 he has been lecturing on computer organization and architecture and parallel programming models. Currently, and since 1997, he is full professor of the Computer Architecture Department at UPC. His research interests cover the areas of processor microarchitecture, multicore architectures and programming models and their architectural support. He has published more than 200 papers in conferences and journals in these topics. He has participated in several research projects in the framework of the European Union and research collaborations with companies. He is associated director for research on computer sciences at the Barcelona Supercomputing Center (BSC-CNS).

 

·          List of publications

·          Full CV (Spanish)

·          Resumee (English)

 

CURRENT TEACHING ACTIVITY (Academic course 2008/09)

·          PCA: Architecture-conscious Programming, FIB Computer Science School

·          Parallel Algorithms and Programming Models (AMPP). Master/PhD course, Computer Architecture and Technology program.

CURRENT RESEARCH AREAS

·          Programming models for multicore and parallel architectures (link)

·          Architecture support for programming models (link)

·          Autonomic systems and eBusiness platforms (link)

CURRENT RESEARCH PROJECTS

·          High-performance Computing V -- Basic research project funded by the Spanish Ministry of Science and Technology TIN2007-60625 (link)

·          BSC-IBM MareIncognito project – Building future Petaflops systems for BSC

·          BSC-Microsoft Research Center – Multicore programming

·          SARC – EU FP6 Scalable Computer Architecture (link)

·          ACOTES – EU FP6 Advanced Compiler Techonologies for Embedded Computing (link)

·          OpenMP 3.0 (link)

UPCOMING CONFERENCES WITH WHICH I AM AFFILIATED

·          MULTIPROG 2009: Second Workshop on Programmability Issues for Multi-Core Computers. Held in conjunction with the 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC). Cyprus, January 25-28, 2009. General co-chair.

·          HiPEAC 2009: 4th International Conference on High Performance and Embedded Architectures and Compilers. Cyprus, January 25-28, 2009. PC member.

·          IWOMP-2009: 5th International Workshop on OpenMP. Dresden, Germany. June 3-5, 2009. PC and SC member.

·          ICS-2009: 23rd International Conference on Supercomputing. IBM T.J. Watson Research Center, New York, USA. June 9-11, 2009. Web and submissions co-chair, SC member.

·          EuroPar 2009: Topic 11 - Multicore Programming. Delft, The Netherlands. August 2009. Topic vice-chair.