[UPC]
[DAC]
[BSC-CNS]

Francisco J. Cazorla's Home Page

Personal Information

Short Bio

Francisco J. Cazorla is the leader of the Operating System/Computer Architecture Interface group at the Barcelona Supercomputing Center(BSC). He received his BS degree in 1999 by the University of Las Palmas de Gran Canaria, and his MS degree in 2001 by the same university (he was awarded best student record in Computer Science in 2001). He also has a PhD (2005) by the Universitat Politecnica de Catalunya(UPC). He has been summer student intern for 5 months with IBM's T.J. Watson Research Center in 2004. His research area focuses on multithreaded architectures for both high-performance and real-time computing systems.

Ph D. Thesis dissertation

Title: Quality of Service for Simultaneous Multithreading Processors [ letter | a4 ]

Publications

The papers below are subject to ACM, IEEE, or other copyrights as noted in the paper's text.
2009
Conferences
 
PACT Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu and Mateo Valero.
ITCA: Inter-Thread Conflict-Aware CPU Accounting for CMPs .
In International Symposium on Parallel Architectures and Compilation Techniques. Raleigh, North Carolina. September 12-16, 2009.
 
ISCA Marco Paolieri, Eduardo Quinones, Francisco J. Cazorla, Guillem Bernat and Mateo Valero.
Hardware Support for WCET Analysis of Multicore Systems .
In International Symposium on Computer Architecture. Austin, USA. June 20-24, 2009.
 
ECRTS Eduardo Quinones, Emery Berger, Guillem Bernat and Francisco J. Cazorla
Using Randomized Caches in Probabilistic Real-Time Systems.
In 21st Euromicro Conference on Real-Time Systems (ECRTS 09). July 1-3, 2009, Dublin, Ireland.
 
Journals
 
OSR 2009 Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Rizos Sakellariou and Mateo Valero.
FlexDCP: a QoS framework for CMP architectures.
In ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors. April 2009.
 
IEEE-CAL Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, and Mateo Valero.
CPU accounting in CMP Processors.
In IEEE Computer Architecture Letters. Volume 9, Issue , 2009.
 
2008
Conferences
 
SBAC-PAD Petar Radojkovic, Vladimir Cakarevic, Javier Verdu, Alex Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky and Malero Valero.
Measuring Operating System Overhead on CMT Processors.
In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil. October 29 - November 1, 2008.
 
SBAC-PAD Jesus Alastruey, Francisco J. Cazorla, Teresa Monreal, Victor Vinals and Mateo Valero.
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors.
In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil. October 29 - November 1, 2008.
 
SC Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose and Mateo Valero.
A Dynamic Scheduler for Balancing HPC Applications.
In International Conference for High Performance Computing, Networking, Storage and Analysis (SC). Austin, USA. November 15-21, 2008.
 
ICPP Carmelo Acosta, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero.
MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors.
In International Conference on Parallel Processing. Portland, Oregon, USA. Oregon, USA. September 2008.
 
ISCA Miquel Pericas, Ruben Gonzalez, Francisco J. Cazorla, Adrian Cristal, Alex Veidenbaum, Daniel A. Jimenez and Mateo Valero.
A two-level Load/Store Queue based on Execution Locality.
In International Symposium on Computer Architecture. Beijing, China. June 21-25, 2008.
 
ISCA Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu and Mateo Valero.
Software-Controlled Priority Characterization of POWER5 Processor.
In International Symposium on Computer Architecture. Beijing, China. June 21-25, 2008.
 
WIOSCA Vladimir Cakarevic, Petar Radojkovic, Javier Verdu, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero.
Understanding the overhead of the spin-lock loop in CMT architectures.
In Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA). Beijing, China. June 22, 2008.
 
CEC P. A. Castillo, J. J. Merelo, M. Moreto, F. J. Cazorla, M. Valero, A. M. Mora, J. L. J. Laredo, and S.A. McKee.
Evolutionary system for prediction and optimization of hardware architecture performance.
In IEEE Congress on Evolutionary Computation (CEC). Hong Kong. June 2008.
 
HiPEAC Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero.
MLP-aware dynamic cache partitioning.
In International Conference on High Performance Embedded Architectures & Compilers. Goterborg, Sweeden. January 27-29, 2008.
 
IPDPS Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Julita Corbalan, Jesus Labarta and Mateo Valero.
Balancing HPC Applications Through Smart Allocation of Resources in MT Processors.
In International Parallel & Distributed Processing Symposium (IPDPS). Miami, Florida, USA. April 14-18, 2008.
 
EVOHOT P. A. Castillo, A. M. Mora, J. J. Merelo, J. L. J. Laredo, M. Moreto, F. J. Cazorla, M. Valero, and S.A. McKee.
Architecture performance prediction using evolutionary artificial neural networks.
In European Workshop on Hardware Optimization Techniques (EVOHot). Napoli, Italy. March 2008.
 
Journals
 
HiPEAC Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero.
Dynamic Cache Partitioning Based on the MLP on Cache Misses.
In Transactions on HiPEAC. Volume 3, Issue 1. May 2008.
 
IEEE-MICRO Kyle J. Nesbit, Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero, and James E. Smith
Multicore Resource Management.
In IEEEmicro,Volume Issue , May/June 2008.
 
ARCS Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa and Mateo Valero.
Scheduling Real-Time Systems With Explicit Resource Allocation Processors.
In International Conference on Architecture of Computing Systems (ARCS). Dresden, Germany. February 25,2008. Lecture Notes in Computer Science. Volume 4934/2008
 
2007
Conferences
 
SPEC-WORKSHOP Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez, and Mateo Valero.
Measuring the Performance of Multithreaded Processors.
In SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)), Austin, USA. January 2007. Schaeffer Award to the technical quality of the paper.
 
CMP-MSI Carmelo Acosta, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero.
Core to Memory Interconexion Implications for Forthcomming On-Chip Multiprocessors.
In Workshop on Chip Multiprocessor Memory Systems and Interconnects (in conjunction with the 13th Annual International Conference on High-Performance Architecture Phoenix, USA. February 2007.
 
IC-SAMOS Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero.
Online Prediction of Applications Cache Utility.
In IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS ), Samos, Greece. July 16-19, 2007.
 
IC-SAMOS Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
On the Problem of Minimizing Workload Execution Time in SMT Processors.
In IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS ), Samos, Greece. July 16-19, 2007.
 
PACT Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliveiro J. Santana, Enrique Fernandez and Mateo Valero.
FAME: FAirly MEasuring Multithreaded Architectures.
In Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania. September 15-19, 2007.
 
PACT Miquel Pericas, Ruben Gonzalez, Adrian Cristal, Francisco J. Cazorla, Daniel A. Jimenez and Mateo Valero.
A Flexible Heterogeneous Multi-Core Architecture.
In Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania. September 15-19, 2007.
 
PACT Miquel Moreto, Francisco J. Cazorla, Alex Ramirez,nd Mateo Valero.
MLP-aware dynamic cache partitioning.
In Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania. September 15-19, 2007.
 
Journals
 
IEEE-CAL Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero.
Explaining Dynamic Cache Partitioning Speed Ups.
In IEEE Computer Architecture Letters. Volume 6, Issue 1, March 2007.
 
2006
Conferences
 
MOBS Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez, and Mateo Valero.
A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures
In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA. June 2006.
 
Journals
 
IEEE-TC Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Predictable Performance in SMT processors: Synergy Between the OS and SMTs.
In IEEE Transaction on Computers. Volume 55, Issue 7, July 2006.
 
2005
Conferences
 
CASES Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Architectural Support for Real-Time Task Scheduling in SMT Processors.
In proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005), San Francisco, USA. September 2005.
 
Journals
 
IEEE-MICRO Adrian Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzi, Tanausu Ramirez, Miquel Pericas, and Mateo Valero
Kilo-instruction Processors: Overcoming the memory wall.
In IEEEmicro,Volume 25 Issue 3, May/June 2005.
 
2004
Conferences
 
MICRO Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Dynamically Controlled Resource Allocation in SMT Processors .
In the 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Portland. December 2004.
 
DSD Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Implicit vs. Explicit Resource Allocation in SMT Processors.
In EUROMICRO Symposium on Digital System Design. Invited Paper. Rennes, France. September 2004.
 
EUSIPCO Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Enabling SMT for Real-Time Embedded Systems.
In 12th European Signal Processing Conference (EUSIPCO). Vienna-Austria. September 2004.
 
WCED Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Approaching a Smart Sharing of Resources in SMT Processors.
In Workshop on Complexity-Effective Design (WCED). Held in conjunction with ISCA., Munich, Germany. June, 2004.
 
IPDPS Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
DCache Warn: an I-Fetch Policy To Increase SMT Efficiency .
In International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, New Mexico. April 2004.
 
ACM-CF Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Predictable Performance in SMT Processors.
In ACM conference on Computing Frontiers (CF-2004), Ischia, Italy. April 2004.
 
Journals
 
IEEE-MICRO Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
QoS for High-Performance SMT Processors in Embedded Systems.
In IEEE Micro . Volume 24, Issue 4, July/August 2004
 
EURO-PAR Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Feasibility of QoS for SMT by Resource Allocation.
In the 10th International Euro-Par Conference. Published in Lecture Notes in Computer Science (LNCS) Volume 3149/2004., Pisa, Italy. September 2004.
 
IJHPCN Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors.
In the International Journal of High Performance Computing and Networking. Special issue on ISHPC-V. Interscience publishers. April 2004
 
2003
Conferences
 
ISHPC Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Improving Memory Latency Aware Fetch Policies for SMT Processors.
In International Symposium on High Performance Computing (ISHPC-V), Tokyo, October 2003. Published in Lecture Notes in Computer Science (LNCS) 2858. Best student paper award.