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Francisco J. Cazorla's Home Page

Personal Information

Short Bio

Francisco J. Cazorla is a researcher in the National Spanish Research Council (CSIC). He is currently the leader of the group on Interaction between the Operating System and the Computer Architecture at BSC ( www.bsc.es/caos ). He is also an asociated researcher in the Computer Architecture Department at the UPC.
He received his BS degree in 1999 by the University of Las Palmas de Gran Canaria, and his MS degree in 2001 by the same university (he was awarded best student record in Computer Science in 2001). He also has a PhD (2005) by the Universitat Politecnica de Catalunya(UPC).
He has worked in industry projects with several processor vendor companies (Intel, IBM, Sun) as well as in European FP6 (SARC) and FP7 Projects (MERASA, PROARTIS). He has led two industrial projects, one with IBM and one with Sun Microsystems (now Oracle). He currently leads the PROARTIS project. He has two submitted patents on the area of hard-real time systems. His research area focuses on multithreaded architectures for both high-performance and real-time systems on which he is co-advising ten PhD theses. He has co-authored over 50 papers in international refereed conferences. He spent five months as a student intern in IBM‘s T.J. Watson in New York in 2004. He is member of HIPEAC and the ARTIST Networks of Excellence.
Francisco J. Cazorla has been selected as one of the 100 Spanish ‘leaders of the future&rsquo according to the May 2009 issue of the Capital Magazine. This issue seeks for the 100 young Spanish citizens that will most influence Spain‘s future in all innovation areas. (www.capital.es). He has also been awarded by the Massachusetts Institute of Technology (MIT), as one of the 10 Spanish young innovators under 35 years, whose technical work has been successfully applied in recent years or has a great potential for development in the coming decades.

Ph D. Thesis dissertation

Title: Quality of Service for Simultaneous Multithreading Processors [ letter | a4 ]

Master Thesis dissertation (in Spanish)

Title: (Implementation and Analysis of the YAGS dynamic brnch predictor: Impllications on Enrergy) Implementación y análisis del mecanismo de predicción dinámica de saltos YAGS: implicaciones energéticas [ a4 ]

Publications

The papers below are subject to ACM, IEEE, or other copyrights as noted in the paper's text.
2012
Conferences
 
ASPLOS Petar Radojkovic, Vladimir Cakarevic, Javier Verdu, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero.
Optimal Task Assignment in Multithreaded Processors: A Statistical Approach.
In Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems. London, UK, March.
 
HiPEAC Petar Radojkovic, Sylvain Girbal, Arnaud Grasset, Eduardo Quinones, Sami Yehia, Francisco J. Cazorla.
On the Evaluation of the Impact of Shared Resources in Multithreaded COTS Processors in Time-Critical Environments.
In 7th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2012). January 23-25 2015. Paris, France.
 
Journals
 
ACM TECS Francisco J. Cazorla, Eduardo Quinones, Tullio Vardanega, Liliana Cucu, Benoit Triquet, Guillem Bernat, Emery Berger, Jaume Abella, Franck Wartel, Michael Houston, Luca Santinelli, Leonidas Kosmidis, Code Lo, Dorin Maxim.>
PROARTIS: Probabilistically Analysable Real-Time Systems.
In ACM Transactions on Embedded Computing Systems. Special issue on Probabilistic Computing,Volume XX Issue XX, To appear 2012.
 
IEEE ToC Alessandro Morari, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose and Mateo Valero>
SMT Malleability in IBM POWER5 and POWER6 Processors.
In IEEE Transaction on Computers, Volume XX Issue XX, To appear 2012.
 
IEEE ToC C. Luque, M. Moreto, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu and M. Valero.
CPU Accounting for Multicore Processors.
In IEEE Transaction on Computers, Volume 61 Issue 2, February 2012.
 
2011
Conferences
 
IOLTS Jaume Abella, Eduardo Quinones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero.
RVC-Based Time-Predictable Faulty Caches for Safety-Critical Systems.
In 17th International On-Line Testing Symposium (IOLTS). July 13-15 2011 . Athens , Greece.
 
IOLTS Jaume Abella, Francisco J. Cazorla, Eduardo Quinones, Dimitris Gizopoulos, Arnaud Grasset, Sami Yehia, Phillipe Bonnot, Riccardo Mariani, Guillem Bernat.
Towards Improved Survivability in Safety-Critical Systems (invited paper).
In 17th International On-Line Testing Symposium (IOLTS). July 13-15 2011 . Athens , Greece.
 
IPDPS Alessandro Morari, Roberto Gioiosa, Robert Wisniewski, Francisco J. Cazorla, Mateo Valero
A Quantitative Analysis of OS Noise.
In 25th IEEE International Parallel & Distributed Processing Symposium (IPDPS). May, 2011. Alaska, USA.
 
RTAS Marco Paolieri, Eduardo Quinones, Frandisco J. Cazorla, Robert I. Davis and Mateo Valero
IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems
In 17th IEEE Real-Time and Embedded Technology and Applications Symposium . April 2011. Chicago, IL, USA.
 
ISORC Marco Paolieri, Eduardo Quinones, Frandisco J. Cazorla1, Julian Wolf, Theo Ungerer, Zlatko Petrov
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-Threaded Hard Real-Time Tasks
In 14th IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing. March, 2011. Newport Beach, CA, USA.
 
HiPEAC Jaume Abella, Eduardo Quinones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero
RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches
In 6th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2011). January, 2011. NHeraklion, Crete (Greece).
 
Journals
 
IEEE CAS Victor Jimenez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu and Pradip Bose.
Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper)
In IEEE Journal of Emerging and Selected Topics in Circuits and Systems,Volume 1 Issue 3, September 2011.
 
ACM TECS Marco Paolieri, Jorg Mische, Stefan Metzlaff, Mike Gerdes, Eduardo Quinones, Sascha Uhrig, Theo Ungerer and Francisco J. Cazorla.
A Hard Real-Time Capable Multi-Core SMT Processor.
In ACM Transactions on Embedded Computing Systems,Volume XX Issue YY, 2011.
 
IEEE Micro V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, C. A. Buyuktosunoglu, P. Bose, M. Valero.
A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications.
In IEEE Micro,Volume XX Issue 99, May/June 2011.
 
2010
Conferences
 
VLSI-SoC V. Jimenez, R. Gioiosa, E. Kursun, F. Cazorla, C. Cher, A. Buyuktosunoglu, P. Bose, M. Valero.
Trends and Techniques for Energy Efficient Architectures. Invited Paper.
In International Conference on VLSI and System-on-Chip (VLSI-SoC). September 2010. Madrid, Spain.
 
PACT V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, C. Cher, A. Buyuktosunoglu, P. Bose, M. Valero.
Power and Thermal Characterization of POWER6 System.
In International Conference on Parallel Architectures and Compilation Techniques (PACT). September 11-15, 2010. Vienna, Austria.
 
ACLD V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, M. Valero.
A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design.
In Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA. June 2010. Sain-Malo, France.
 
IFMT K. Kedzierski, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, M. Valero.
Power and Performance Aware Reconfigurable Cache for CMPs.
In Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA. June 2010. Sain-Malo, France.
 
CF Miquel Moreto, Francisco J. Cazorla, Rizos Sakellariou and Mateo Valero.
Load Balancing Using Dynamic Cache Allocation.
In ACM International Conference on Computing Frontiers (CF). May 2010. Bertinoro, Italy.
 
IPDPS Kamil Kedzierski, Miquel Moreto, Francisco J. Cazorla and Mateo Valero.
Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies.
In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS) April 19-23, 2010. ATLANTA (Georgia) USA .
 
PPoPP Petar Radojkovic, Vladimir Cakarevic, Javier Verdu, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero.
Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems.
In 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming January 2010, Bangalore, India.
 
Journals
 
IEEE-ToC Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez, and Mateo Valero.
On the Problem of Evaluating the Performance of Multiprogrammed Workloads.
In IEEE Transactions on Computers,Volume 59 Issue 12, Dec 2010.
 
IEEE-MICRO Theo Ungerer, Francisco J. Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quinones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Casse, Sascha Uhrig, Irakli Guliashvili, Michael Houston, Florian Kluge, Stefan Metzlaff, Jorg Mische.
MERASA: Multicore Execution of Hard Real-Time Applications Supporting Analyzability.
In IEEEmicro,Volume 30 Issue 5, Sep/Oct 2010.
 
2009
Conferences
 
MICRO Vladimir Cakarevic, Petar Radojkovic, Javier Verdu, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero.
Characterizing the resource-sharing levels in the UltraSPARC T2 Processor.
In 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). New York City, USA, December 12-16, 2009.
 
SBAC-PAD Carmelo Acosta, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero.
Thread to Core Assignment in SMT On-Chip Multiprocessors.
In 21st Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Sao Paulo, Brazil, October 28-31, 2009.
 
RePP Marco Paolieri, Eduardo Quinones, Francisco J. Cazorla and Mateo Valero.
Efficient Execution of Mixed Application Workloads in a Hard Real-Time.
In Workshop on Reconciling Performance with Predictability (RePP) Oct. 15, 2009, during the ESWEEK, in Grenoble, France.
 
PACT Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu and Mateo Valero.
ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs.
In International Symposium on Parallel Architectures and Compilation Techniques. Raleigh, North Carolina. September 12-16, 2009.
 
PACT (Poster) Kamil Kedzierski, Miquel Moreto, Francisco J. Cazorla and Mateo Valero.
pseudo-LRU based Cache Partitioning Algorithms .
In International Symposium on Parallel Architectures and Compilation Techniques. Raleigh, North Carolina. September 12-16, 2009.
 
ISCA Marco Paolieri, Eduardo Quinones, Francisco J. Cazorla, Guillem Bernat and Mateo Valero.
Hardware Support for WCET Analysis of Multicore Systems .
In International Symposium on Computer Architecture. Austin, USA. June 20-24, 2009.
 
ECRTS Eduardo Quinones, Emery Berger, Guillem Bernat and Francisco J. Cazorla
Using Randomized Caches in Probabilistic Real-Time Systems.
In 21st Euromicro Conference on Real-Time Systems (ECRTS 09). July 1-3, 2009, Dublin, Ireland.
 
Journals
 
OSR 2009 Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Rizos Sakellariou and Mateo Valero.
FlexDCP: a QoS framework for CMP architectures.
In ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors. April 2009.
 
IEEE-CAL Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, and Mateo Valero.
CPU accounting in CMP Processors.
In IEEE Computer Architecture Letters. Volume 9, Issue 2, 2009.
 
IEEE-ESL Marco Paolieri, Eduardo Quinones, Francisco J. Cazorla and Mateo Valero.
An Analyzable Memory Controller for Hard Real-Time CMPs .
In IEEE Embedded Systems Letters Volume 1, Issue 4
 
2008
Conferences
 
SBAC-PAD Petar Radojkovic, Vladimir Cakarevic, Javier Verdu, Alex Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky and Malero Valero.
Measuring Operating System Overhead on CMT Processors.
In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil. October 29 - November 1, 2008.
 
SBAC-PAD Jesus Alastruey, Francisco J. Cazorla, Teresa Monreal, Victor Vinals and Mateo Valero.
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors.
In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil. October 29 - November 1, 2008.
 
SC Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose and Mateo Valero.
A Dynamic Scheduler for Balancing HPC Applications.
In International Conference for High Performance Computing, Networking, Storage and Analysis (SC). Austin, USA. November 15-21, 2008.
 
ICPP Carmelo Acosta, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero.
MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors.
In International Conference on Parallel Processing. Portland, Oregon, USA. Oregon, USA. September 2008.
 
ISCA Miquel Pericas, Ruben Gonzalez, Francisco J. Cazorla, Adrian Cristal, Alex Veidenbaum, Daniel A. Jimenez and Mateo Valero.
A two-level Load/Store Queue based on Execution Locality.
In International Symposium on Computer Architecture. Beijing, China. June 21-25, 2008.
 
ISCA Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu and Mateo Valero.
Software-Controlled Priority Characterization of POWER5 Processor.
In International Symposium on Computer Architecture. Beijing, China. June 21-25, 2008.
 
WIOSCA Vladimir Cakarevic, Petar Radojkovic, Javier Verdu, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero.
Understanding the overhead of the spin-lock loop in CMT architectures.
In Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA). Beijing, China. June 22, 2008.
 
CEC P. A. Castillo, J. J. Merelo, M. Moreto, F. J. Cazorla, M. Valero, A. M. Mora, J. L. J. Laredo, and S.A. McKee.
Evolutionary system for prediction and optimization of hardware architecture performance.
In IEEE Congress on Evolutionary Computation (CEC). Hong Kong. June 2008.
 
HiPEAC Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero.
MLP-aware dynamic cache partitioning.
In International Conference on High Performance Embedded Architectures & Compilers. Goterborg, Sweeden. January 27-29, 2008.
 
IPDPS Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Julita Corbalan, Jesus Labarta and Mateo Valero.
Balancing HPC Applications Through Smart Allocation of Resources in MT Processors.
In International Parallel & Distributed Processing Symposium (IPDPS). Miami, Florida, USA. April 14-18, 2008.
 
EVOHOT P. A. Castillo, A. M. Mora, J. J. Merelo, J. L. J. Laredo, M. Moreto, F. J. Cazorla, M. Valero, and S.A. McKee.
Architecture performance prediction using evolutionary artificial neural networks.
In European Workshop on Hardware Optimization Techniques (EVOHot). Napoli, Italy. March 2008.
 
Journals
 
HiPEAC Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero.
Dynamic Cache Partitioning Based on the MLP on Cache Misses.
In Transactions on HiPEAC. Volume 3, Issue 1. May 2008.
 
IEEE-MICRO Kyle J. Nesbit, Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero, and James E. Smith
Multicore Resource Management.
In IEEEmicro,Volume Issue , May/June 2008.
 
ARCS Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa and Mateo Valero.
Scheduling Real-Time Systems With Explicit Resource Allocation Processors.
In International Conference on Architecture of Computing Systems (ARCS). Dresden, Germany. February 25,2008. Lecture Notes in Computer Science. Volume 4934/2008
 
2007
Conferences
 
SPEC-WORKSHOP Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez, and Mateo Valero.
Measuring the Performance of Multithreaded Processors.
In SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)), Austin, USA. January 2007. Schaeffer Award to the technical quality of the paper.
 
CMP-MSI Carmelo Acosta, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero.
Core to Memory Interconexion Implications for Forthcomming On-Chip Multiprocessors.
In Workshop on Chip Multiprocessor Memory Systems and Interconnects (in conjunction with the 13th Annual International Conference on High-Performance Architecture Phoenix, USA. February 2007.
 
IC-SAMOS Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero.
Online Prediction of Applications Cache Utility.
In IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS ), Samos, Greece. July 16-19, 2007.
 
IC-SAMOS Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
On the Problem of Minimizing Workload Execution Time in SMT Processors.
In IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS ), Samos, Greece. July 16-19, 2007.
 
PACT Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliveiro J. Santana, Enrique Fernandez and Mateo Valero.
FAME: FAirly MEasuring Multithreaded Architectures.
In Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania. September 15-19, 2007.
 
PACT Miquel Pericas, Ruben Gonzalez, Adrian Cristal, Francisco J. Cazorla, Daniel A. Jimenez and Mateo Valero.
A Flexible Heterogeneous Multi-Core Architecture.
In Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania. September 15-19, 2007.
 
PACT (Poster) Miquel Moreto, Francisco J. Cazorla, Alex Ramirez,nd Mateo Valero.
MLP-aware dynamic cache partitioning.
In Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania. September 15-19, 2007.
 
Journals
 
IEEE-CAL Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero.
Explaining Dynamic Cache Partitioning Speed Ups.
In IEEE Computer Architecture Letters. Volume 6, Issue 1, March 2007.
 
2006
Conferences
 
MOBS Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez, and Mateo Valero.
A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures
In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA. June 2006.
 
Journals
 
IEEE-TC Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Predictable Performance in SMT processors: Synergy Between the OS and SMTs.
In IEEE Transaction on Computers. Volume 55, Issue 7, July 2006.
 
2005
Conferences
 
CASES Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Architectural Support for Real-Time Task Scheduling in SMT Processors.
In proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005), San Francisco, USA. September 2005.
 
Journals
 
IEEE-MICRO Adrian Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzi, Tanausu Ramirez, Miquel Pericas, and Mateo Valero
Kilo-instruction Processors: Overcoming the memory wall.
In IEEEmicro,Volume 25 Issue 3, May/June 2005.
 
2004
Conferences
 
MICRO Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Dynamically Controlled Resource Allocation in SMT Processors .
In the 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Portland. December 2004.
 
DSD Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Implicit vs. Explicit Resource Allocation in SMT Processors.
In EUROMICRO Symposium on Digital System Design. Invited Paper. Rennes, France. September 2004.
 
EUSIPCO Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Enabling SMT for Real-Time Embedded Systems.
In 12th European Signal Processing Conference (EUSIPCO). Vienna-Austria. September 2004.
 
WCED Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Approaching a Smart Sharing of Resources in SMT Processors.
In Workshop on Complexity-Effective Design (WCED). Held in conjunction with ISCA., Munich, Germany. June, 2004.
 
IPDPS Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
DCache Warn: an I-Fetch Policy To Increase SMT Efficiency .
In International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, New Mexico. April 2004.
 
ACM-CF Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Predictable Performance in SMT Processors.
In ACM conference on Computing Frontiers (CF-2004), Ischia, Italy. April 2004.
 
Journals
 
IEEE-MICRO Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
QoS for High-Performance SMT Processors in Embedded Systems.
In IEEE Micro . Volume 24, Issue 4, July/August 2004
 
EURO-PAR Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Feasibility of QoS for SMT by Resource Allocation.
In the 10th International Euro-Par Conference. Published in Lecture Notes in Computer Science (LNCS) Volume 3149/2004., Pisa, Italy. September 2004.
 
IJHPCN Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors.
In the International Journal of High Performance Computing and Networking. Special issue on ISHPC-V. Interscience publishers. April 2004
 
2003
Conferences
 
ISHPC Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero.
Improving Memory Latency Aware Fetch Policies for SMT Processors.
In International Symposium on High Performance Computing (ISHPC-V), Tokyo, October 2003. Published in Lecture Notes in Computer Science (LNCS) 2858. Best student paper award.