[Papers] |
[Awards] |
[Patents] |
[Participation in projects] |
[Program committees] |
[Participation in reviews] |
[Attended conferences] |
REAL TIME |
|
"Measurement-Based Probabilistic Timing Analysis for Multi-path Programs" (not public yet) Liliana Cucu-Grosjean, Luca Santinelli, Michael Houston, Code Lo, Tullio Vardanega, Leonidas Kosmidis, Jaume Abella, Enrico Mezzeti, Eduardo Quinones, Francisco J. Cazorla ECRTS 2012 24th Euromicro Conference on Real-Time Systems Pisa (Italy), July 11-13 2012 |
|
"Reliability and Power in Safety-Critical Systems: A Hardware Perspective" (invited talk) Jaume Abella HiPEAC CSW 2011 HiPEAC Computing Systems Week Barcelona (Spain), November 2-4 2011 |
|
"PROARTIS: Probabilistically Analysable Real-Time Systems" (not public yet) Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu, Benoit Triquet, Guillem Bernat, Emery Berger, Jaume Abella, Franck Wartel, Michael Houston, Luca Santinelli, Leonidas Kosmidis, Code Lo, Dorin Maxim ACM Transactions on Embedded Computing Systems (TECS) Special issue on Probabilistic Embedded Computing to appear |
|
"Results from PROARTIS" (invited talk) Francisco J. Cazorla, Jaume Abella ADCSS 2011 European Space Agency (ESA) Workshop on Avionics Data, Control and Software Systems (ADCSS) Noordwijk (The Netherlands), October 25-27 2011 |
|
"Towards Improved Survivability in Safety-Critical Systems" (invited paper) Jaume Abella, Francisco J. Cazorla, Eduardo Quiñones, Dimitris Gizopoulos, Arnaud Grasset, Sami Yehia, Phillipe Bonnot, Riccardo Mariani, Guillem Bernat IOLTS 2011 17th International On-Line Testing Symposium Athens (Greece), July 13-15 2011 |
|
"RVC-Based Time-Predictable Faulty Caches for Safety-Critical Systems" Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero IOLTS 2011 17th International On-Line Testing Symposium Athens (Greece), July 13-15 2011 |
|
"Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems" Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Mateo Valero ACM SIGBED Review Special Interest Group on Embedded Systems Review Newsletter September 2011 ECRTS WiP 2011 23rd Euromicro Conference on Real-Time Systems - Work in Progress session Porto (Portugal), July 6-8 2011 |
|
"RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches" Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero HiPEAC 2011 6th International Conference on High-Performance Embedded Architectures and Compilers Heraklion, Crete (Greece), January 24-26 2011 |
|
"Use of Randomized Caches in Hard Real-Time Systems" (poster) Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Guillem Bernat, Emery D. Berger ACACES 2010 6th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems Terrassa (Spain), July 11-17 2010 |
|
"Hard Real-Time Capable Multicore Processors for Space Applications" (poster) Miquel Moreto, Marco Paolieri, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla NPI 2010 1st Networking/Partnering Day at the European Space Agency Noordwijk (The Netherlands), January 28 2010 |
RESILIENCE |
|
"Control-Flow Recovery Validation Using Microarchitectural Invariants" Javier Carretero, Jaume Abella, Xavier Vera, Pedro Chaparro DFT 2011 26th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems Vancouver (Canada), October 3 - 5 2011 |
|
"Design of Complex Circuits Using the Via-Configurable Transistor Array Regular Layout Fabric" Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González SOCC 2011 24th IEEE International SoC Conference Taipei (Taiwan), September 26 - 28 2011 |
|
"Implementing End-to-End Register Data-Flow Continuous Self-Test" Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González IEEE Transactions on Computers August 2011 |
|
"Fast Time-to-Market with Via-Configurable Transistor Array Regular Fabric: a Delay-Locked Loop Design Case Study" Marc Pons, Enrique Barajas, Diego Mateo, José Luis González, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González DTIS 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era Athens (Greece), April 6 - 8 2011 |
|
"Hardware/Software-Based Diagnosis of Load-Store Queues Using Expandable Activity Logs" Javier Carretero, Xavier Vera, Jaume Abella, Tanausú Ramírez, Matteo Monchiero, Antonio González HPCA 2011 17th International Symposium on High-Performance Computer Architecture San Antonio (Texas), January 12 - 16 2011 |
|
"VCTA: A Via-Configurable Transistor Array Regular Fabric" Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González VLSI-SoC 2010 18th International Conference on VLSI and System-on-Chip Madrid (Spain), September 27 - 29 2010 |
|
"Microarchitectural On-line Testing for Failure Detection in Memory Order Buffers" Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella IEEE Transactions on Computers Special Issue on System Level Design of Reliable Architectures May 2010 |
|
"The Split Register File" Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero DATE 2010 13th Design, Automation and Test in Europe Conference Dresden (Germany), March 8-12 2010 |
|
"Electromigration for Microarchitects" Jaume Abella, Xavier Vera ACM Computing Surveys February 2010 |
|
"High-Performance Low-Vcc In-Order Core" Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González HPCA 2010 16th International Symposium on High-Performance Computer Architecture Bangalore (India), January 11 - 14 2010 |
|
"Selective Replication: a Lightweight Technique for Soft Errors" Xavier Vera, Javier Carretero, Jaume Abella, Antonio González ACM Transactions on Computer Systems December 2009 |
|
"Low Vccmin Fault-Tolerant Cache with Highly Predictable Performance" Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González MICRO 2009 42nd International Symposium on Microarchitecture New York (New York), December 14 - 16 2009 |
|
"Online Error Detection and Correction of Erratic Bits in Register Files" Xavier Vera, Jaume Abella, Javier Carretero, Pedro Chaparro, Antonio González IOLTS 2009 15th International On-Line Testing Symposium Lisbon (Portugal), June 24 - 27 2009 |
|
"End-to-End Register Data-Flow Continuous Self-Test" Javier Carretero, Pedro Chaparro, Jaume Abella, Xavier Vera, Antonio González ISCA 2009 36th International Symposium on Computer Architecture Austin (Texas), June 22 - 24 2009 A version of this paper has been published in DTTC 2008 Intel Design and Test Technolgy Conference (internal Intel conference) |
|
"A Low-Overhead Technique to Protect the Issue Control Logic against Soft Errors" Javier Carretero, Xavier Vera, Jaume Abella, Pedro Chaparro, Antonio González SELSE 2009 5th Workshop on Silicon Errors in Logic - System Effects Stanford University (California), March 24 - 25 2009 |
|
"Refueling: Preventing Wire Degradation due to Electromigration" Jaume Abella, Xavier Vera, Osman Unsal, Oguz Ergin, Antonio González, James W. Tschanz IEEE Micro Special Issue on Existential Architectures - The Metaphysics of Computer Design November-December 2008 |
|
"On-line Failure Detection in Memory Order Buffers" Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella ITC 2008 International Test Conference Santa Clara (California), October 28 - 30 2008 |
|
"Issue System Protection Mechanisms" Pedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera ICCD 2008 26th International Conference on Computer Design Lake Tahoe (California), October 12 - 15 2008 |
|
"Dynamic Errors: Symptoms and Solutions" (invited talk in the Industrial Track) Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio Gonzalez EUROPAR 2008 14th International Euro-Par Conference. European Conference on Parallel and Distributed Computing Las Palmas de Gran Canaria (Spain), August 27 - 29 2008 |
|
"On-Line Failure Detection and Confinement in Caches" Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González IOLTS 2008 14th International On-Line Testing Symposium Rodhes Island (Greece), July 7 - 9 2008 |
|
"Soft-Error Protection Mechanisms for In-Order Cores" Pedro Chaparro, Javier Carretero, Jaume Abella, Xavier Vera SELSE 2008 4th Workshop on Silicon Errors in Logic - System Effects Austin (Texas), March 26 - 27 2008 |
|
"Penelope: the NBTI-Aware Processor" (powerpoint slides) Jaume Abella, Xavier Vera, Antonio González MICRO 2007 40th International Symposium on Microarchitecture Chicago (Illinois), December 3 - 5 2007 A version of this paper has been published in DTTC 2007 Intel Design and Test Technolgy Conference (internal Intel conference) |
|
"Via-Configurable Transistors Array: A Regular Design Technique to Improve ICs Yield" Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González DFM&Y 2007 2nd International Workshop on Design for Manufacturability and Yield (in conjunction with ITC'07) Santa Clara (California), October 25 - 26 2007 |
|
"Surviving Errors in Multi-Core Environments" (powerpoint slides) Presentation in the Special session on Reconfiguration and Fault Tolerance in Future Massively Parallel Multi-Core Chips Xavier Vera, Jaume Abella IOLTS 2007 13th International On-Line Testing Symposium Hersonissos-Heraklion, Crete (Greece), July 9 - 11 2007 |
|
"Fuse: A Technique to Anticipate Failures due to Degradation in ALUs" Jaume Abella, Xavier Vera, Osman Unsal, Oguz Ergin, Antonio González IOLTS 2007 13th International On-Line Testing Symposium Hersonissos-Heraklion, Crete (Greece), July 9 - 11 2007 |
|
"NBTI-Resilient Memory Cells with NAND Gates for Highly-Ported Structures" (powerpoint slides) Jaume Abella, Xavier Vera, Osman Unsal, Antonio González WDSN 2007 Workshop on Dependable and Secure Nanocomputing (in conjunction with DSN'07) DSN 2007 Also a poster in the 37th Dependable Systems and Networks Edinburgh (UK), June 28 2007 |
|
"Reducing Soft Error Vulnerability of Data Caches" Xavier Vera, Jaume Abella, Antonio González, Ronny Ronen SELSE 2007 3rd Workshop on Silicon Errors in Logic - System Effects Austin (Texas), April 3 - 4 2007 |
|
"Checker Cluster for Soft and Timing Error Detection and Recovery" (powerpoint slides) Xavier Vera, Jaume Abella, Osman Unsal, Antonio González, Oguz Ergin SELSE 2006 2nd Workshop on System Effects of Logic Soft Errors Urbana-Champaign (Illinois), April 11 - 12 2006 |
LOW POWER |
|
"ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches" Bojan Maric, Jaume Abella, Mateo Valero GLSVLSI 2012 22nd Great Lakes Symposium on VLSI Salt Lake City (Utah), May 3-4 2012 |
|
"Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches" (short paper and poster) Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero CF 2011 8th International Conference on Computing Frontiers Ischia (Italy), May 3-5 2011 |
|
"Energy-Efficient Register Caching with Compiler Assistance" Tim Jones, Michael F.P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin ACM TACO ACM Transactions on Architecture and Code Optimization October 2009 |
|
"Exploring the Limits of Early Register Release: Exploiting Compiler Analysis" Tim Jones, Michael F.P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin ACM TACO 2009 ACM Transactions on Architecture and Code Optimization September 2009 |
|
"Compiler Directed Issue Queue Energy Reduction" Tim Jones, Michael F.P. O'Boyle, Jaume Abella, Antonio González Transactions on HiPEAC Transactions on High-Performance Embedded Architectures and Compilers Volume 4, Issue 1, February 2009 |
|
"Designing Efficient Processors Using Compiler-Directed Optimisations" Timothy Jones, Michael F.P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin INTERACT 2007 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (in conjunction with HPCA'07) Phoenix (Arizona), February 11 2007 |
|
"Heterogeneous Way-Size Cache" Jaume Abella, Antonio González ICS 2006 20th International Conference on Supercomputing Cairns (Australia), June 28 - 30 2006 |
|
"SAMIE-LSQ: Set-Associative Multiple-Instruction Entry Load/Store Queue" Jaume Abella, Antonio González IPDPS 2006 20th International Parallel and Distributed Processing Symposium Rhodes Island (Greece), April 25 - 29 2006 |
|
"A Heterogeneous Multi-Module Data Cache for VLIW Processors" (powerpoint slides) Enric Gibert, Jaume Abella, Xavier Vera, Jesús Sánchez, Antonio González EPIC 2006 5th Explicitly Parallel Instruction Computing Workshop (in conjunction with CGO'06) New York (New York), March 26 2006 |
|
"Compiler Directed Early Register Release" Timothy Jones, Michael F.P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin PACT 2005 14th International Conference on Parallel Architectures and Compilation Techniques Saint Louis (Missouri), September 17 - 19 2005 |
|
"Variable-Based Multi-module Data Caches for Clustered VLIW Processors" Enric Gibert, Jaume Abella, Jesús Sánchez, Xavier Vera, Antonio González PACT 2005 14th International Conference on Parallel Architectures and Compilation Techniques Saint Louis (Missouri), September 17 - 19 2005 |
|
"Software Assisted Issue Queue Power Reduction" Timothy Jones, Michael F.P. O'Boyle, Jaume Abella, Antonio González HPCA 2005 11th International Symposium on High Performance Computer Architecture San Francisco (California), February 12 - 16 2005 |
|
"Inherently Workload-Balanced Clustered Microarchitecture" (powerpoint slides) Jaume Abella, Antonio González IPDPS 2005 19th International Parallel and Distributed Processing Symposium Denver (Colorado), April 4 - 8 2005 |
|
"IATAC: A Smart Predictor to Turn-off L2 Cache Lines" Jaume Abella, Antonio González, Xavier Vera, Michael F.P. O'Boyle ACM TACO 2005 ACM Transactions on Architecture and Code Optimization March 2005 |
|
Poster: "Power and Complexity Aware Microarchitectures" (powerpoint slides) Jaume Abella, Ramon Canal, Antonio González IAF-EMEA 2004 9th Intel EMEA Academic Forum Barcelona (Spain), April 20 - 22 2004 |
|
"Low-Complexity Distributed Issue Queue" (powerpoint slides) Jaume Abella, Antonio González HPCA 2004 10th International Symposium on High Performance Computer Architecture Madrid (Spain), February 14 - 18 2004 |
|
"Power-Aware Adaptive Issue Queue and Register File" (powerpoint slides) Jaume Abella, Antonio González HiPC 2003 International Conference on High Performance Computing Hyderabad (India), December 17 - 20 2003 |
|
"Power- and Complexity-Aware Issue Queue Designs" Jaume Abella, Ramon Canal, Antonio González IEEE Micro Special Issue on Power- and Complexity-Aware Design September-October 2003 |
|
"On Reducing Register Pressure and Energy in Multiple-Banked Register Files" (powerpoint slides) Jaume Abella, Antonio González ICCD 2003 21st International Conference on Computer Design San Jose (California), October 13 - 15 2003 |
|
"Power Efficient Data Cache Designs" (powerpoint slides) Jaume Abella, Antonio González ICCD 2003 21st International Conference on Computer Design San Jose (California), October 13 - 15 2003 |
COMPILATION |
|
"An Accurate Cost Model for Guiding Data Locality Transformations" Xavier Vera, Jaume Abella, Josep Llosa, Antonio González ACM Transactions on Programming Languages and Systems (TOPLAS) Volume 27, Issue 5, September 2005 |
|
"Optimizing Program Locality through CMEs and GAs" Xavier Vera, Jaume Abella, Antonio González, Josep Llosa PACT 2003 12th International Conference on Parallel Architectures and Compilation Techniques New Orleans (Louisiana), September 27 - October 1 2003 |
|
"Near-Optimal Loop Tiling by means of Cache Miss Equations and Genetic Algorithms" (also available powerpoint slides) Jaume Abella, Antonio González, Josep Llosa, Xavier Vera CRTPC 2002 Workshop on Compiler/Runtime Techniques for Parallel Computing (in conjunction with ICPP02) Vancouver (Canada), August 18-21 2002 |
|
"Near-Optimal Loop Tiling by means of Cache Miss Equations and Genetic Algorithms" (Jornadas version) (also available powerpoint slides) Jaume Abella, Antonio González, Josep Llosa, Xavier Vera XIII Jornadas de Paralelismo Lleida (Spain), September 9-11 2002. |
OTHERS |
|
"Online Performance Prediction in Processors with DVFS Capabilities" (poster) Qixiao Liu, Miquel Moreto, Jaume Abella, Francisco J. Cazorla ACACES 2011 7th International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems Fiuggi (Italy), July 10-16 2011 |
|
"The MHAOTEU Toolset" Jaume Abella, Sid Ahmed Ali Touati, Alan Anderson, Carlos Ciuraneta, Josep M. Codina, Min Dai, Christine Eisenbeis, Grigori Fursin, Antonio González, Josep Llosa, Michael O'Boyle, Andry Randrianatoavina, Jesus Sánchez, Olivier Temam, Xavier Vera, Gregory Watts IMACS 2000 Agent-Based Simulation, Planning and Control of the 16th IMACS World Congress 2000, on Scientific Computation, Applied Mathematics and Simulation Lausanne (Switzerland), August 21-25 2000 |
|
"On-line Testing for Decode Logic" Pedro Chaparro, Jaume Abella, Xavier Vera, Javier Carretero USPTO Patent No. 8,069,376, issued 29-November-2011 |
|
"Memory Apparatuses with Low Supply Voltages" Jaume Abella, Xavier Vera, Javier Carretero, Pedro Chaparro, Antonio González USPTO Application No. 20100115224, Patent No. --------, published 6-May-2010 |
|
"Disabling Cache Portions During Low Voltage Operations" Chris Wilkerson, Muhammad M. Khellah, Vivek De, Ming Y. Zhang, Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González International Application No. PCT/US2009/058026 USPTO Patent No. 8,103,830, issued 24-January-2012 ("Disabling Cache Portions During Low Voltage Operations") Japan Application No. 2011-528093, Patent No. --------, filed 15-February-2011 ("Disabling Cache Portions During Low Voltage Operations") China Application No. 200910222700, Patent No. --------, published 26-May-2010 ("Disabling Cache Portions During Low Voltage Operations") Republic of Korea Patent No. 1020117007404, Patent No. --------, published 9-June-2011 ("Disabling Cache Portions During Low Voltage Operations") |
|
"Improved Capacity Register File" Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera USPTO Application No. 20090150649, Patent No. --------, published 11-June-2009 |
|
"Mechanism for Soft Error Detection and Recovery in Issue Queues" Pedro Chaparro, Xavier Vera, Jaume Abella, Javier Carretero USPTO Application No. 20090150653, Patent No. --------, published 11-June-2009 |
|
"Correcting Intermittent Errors in Data Storage Structures" Jaume Abella, Xavier Vera, Javier Carretero USPTO Patent No. 7,747,913, issued 29-June-2010 |
|
"Protecting Data Storage Structures from Intermittent Errors" Xavier Vera, Jaume Abella, Javier Carretero, Antonio González USPTO Application No. 20090037783, Patent No. --------, published 5-February-2009 |
|
"Reduction of Effect of Ageing on Registers" Jaume Abella, Xavier Vera, Antonio González International Application No. PCT/ES2006/070168 USPTO Application No. 20090150656, Patent No. --------, published 11-June-2009 ("Reducing Aging Effect on Registers") |
|
"Memory Content Inverting to Minimize NBTI Effects" Jaume Abella, Xavier Vera, Javier Carretero, Jose-Alejandro Piñeiro, Antonio González USPTO Patent No. 7,577,015, issued 18-August-2009 |
|
"Cache Sharing Based Thread Control" Jaideep Moses, Jose-Alejandro Piñeiro, Don Newell, Enric Gibert, Ravishankar Iyer, Jaume Abella, Josep M. Codina, Ramesh Illikkal, Pedro López, Fernando Latorre, Srihari Makineni, Antonio González USPTO Patent No. 7,895,415, issued 22-February-2011 |
|
"Selectively Protecting a Register File" Xavier Vera, Jaume Abella, Jose-Alejandro Piñeiro, Antonio González, Ronny Ronen USPTO Patent No. 7,689,804, issued 30-March-2010 |
|
"NBTI-Resistant Memory Cells with NAND Gates" Jaume Abella, Xavier Vera, Osman Unsal, Antonio González International Application No. PCT/ES2006/000542 USPTO Patent No. 7,447,054, issued 4-November-2008 ("NBTI-Resilient Memory Cells with NAND Gates") Germany Application No. 1120060040022, Patent No. --------, filed 23-February-2009 ("NBTI-resistente Speicherzellen mit Nand-Gliedern") Japan Application No. 2009-529720, Patent No. --------, published 12-February-2010 ("NBTI-Resistant Memory Cells with NAND Gates") China Application No. 200680055721, Patent No. --------, published 12-August-2009 ("NBTI-Resistant Memory Cells with NAND Gates") Republic of Korea Patent No. 1010590620000, issued 31-May-2011 ("NBTI-Resistant Memory Cells with NAND Gates") |
|
"Detection of Transient Errors by Means of New Selective Implementation" Xavier Vera, Oguz Ergin, Osman Unsal, Jaume Abella, Antonio González International Application No. PCT/ES2006/070041 USPTO Patent No. 8,090,996, issued 3-January-2012 ("Detecting Soft Errors Via Selective Re-execution") China Application No. 200680054141, Patent No. --------, published 22-April-2009 ("Detection of Transient Errors by Means of New Selective Implementation") Republic of Korea Patent No. 1009905910000, issued 30-July-2010 ("Detection of Transient Errors by Means of New Selective Implementation") |
|
"Improvement in the Reliability of a Multi-Core Processor" Xavier Vera, Osman Unsal, Oguz Ergin, Jaume Abella, Antonio González International Application No. PCT/ES2006/070021 USPTO Patent No. 8,074,110, issued 6-December-2011 ("Enhancing Reliability of a Many-Core Processor") Japan Application No. 2008-551806, Patent No. --------, published 2-July-2009 ("Improvement in the Reliability of a Multi-Core Processor") China Application No. 200680053450, Patent No. --------, published 18-March-2009 ("Improvement in the Reliability of a Multi-Core Processor") |
|
"Dynamic Estimation of the Lifetime of a Semiconductor Device" Xavier Vera, Jaume Abella, Osman Unsal, Oguz Ergin, Antonio González International Application No. PCT/ES2005/070188 USPTO Patent No. 8,151,094, issued 3-April-2012 ("Dynamically Estimating Lifetime of a Semiconductor Device") China Application No. 200580052138 , Patent No. --------, published 26-November-2008 ("Dynamic Estimation of Semiconductor Device Life") |
VeTeSSVeTeSS: Verification and Testing to Support Functional Safety StandardsARTEMIS project number 295311 From 1-May-2012 until 30-April-2015 |
|
No deliverables yet |
PARMERASAMulti-Core Execution of Parallelised Hard Real-Time Applications Supporting AnalysabilityFP7-ICT project number 287519 From 1-October-2011 until 31-September-2014 |
|
No deliverables yet |
PROARTISProbabilistically Analysable Real-Time SystemsFP7-ICT project number 249100 From 1-February-2010 until 31-July-2013 |
|
D1.2 Platform Design Guidelines for Single Core Year 8/2010 - 4/2012 Authors: Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu-Grosjean, Guillem Bernat, Benoit Triquet, Jaume Abella, Leonidas Kosmidis, Emery Berger, Elisa Turrini, Enrico Mezzetti, Andrea Baldovin, Luca Santinelli, Code Lo, Dorin Maxim, Mike Houston, Ian Broster, Mike Towers, Franck Wartel Barcelona Supercomputing Center, University of Padova, INRIA, Rapita Systems Ltd., Airbus |
|
D2.2 Software Design/Programming Guides for Single Core Year 8/2010 - 4/2012 Authors: Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu-Grosjean, Guillem Bernat, Benoit Triquet, Jaume Abella, Leonidas Kosmidis, Emery Berger, Elisa Turrini, Enrico Mezzetti, Andrea Baldovin, Luca Santinelli, Code Lo, Dorin Maxim, Mike Houston, Ian Broster, Mike Towers, Franck Wartel Barcelona Supercomputing Center, University of Padova, INRIA, Rapita Systems Ltd., Airbus |
|
D2.3 Certification Arguments Guidelines (Initial Draft) Year 8/2010 - 4/2012 Authors: Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu-Grosjean, Guillem Bernat, Benoit Triquet, Jaume Abella, Leonidas Kosmidis, Emery Berger, Elisa Turrini, Enrico Mezzetti, Andrea Baldovin, Luca Santinelli, Code Lo, Dorin Maxim, Mike Houston, Ian Broster, Mike Towers, Franck Wartel Barcelona Supercomputing Center, University of Padova, INRIA, Rapita Systems Ltd., Airbus |
|
D3.4 Probabilistic and Statistical Techniques for Timing Analysis in Single Core Year 8/2010 - 4/2012 Authors: Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu-Grosjean, Guillem Bernat, Benoit Triquet, Jaume Abella, Leonidas Kosmidis, Emery Berger, Elisa Turrini, Enrico Mezzetti, Andrea Baldovin, Luca Santinelli, Code Lo, Dorin Maxim, Mike Houston, Ian Broster, Mike Towers, Franck Wartel Barcelona Supercomputing Center, University of Padova, INRIA, Rapita Systems Ltd., Airbus |
|
D4.3 Single Core Case Study Year 8/2010 - 4/2012 Authors: Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu-Grosjean, Guillem Bernat, Benoit Triquet, Jaume Abella, Leonidas Kosmidis, Emery Berger, Elisa Turrini, Enrico Mezzetti, Andrea Baldovin, Luca Santinelli, Code Lo, Dorin Maxim, Mike Houston, Ian Broster, Mike Towers, Franck Wartel Barcelona Supercomputing Center, University of Padova, INRIA, Rapita Systems Ltd., Airbus |
|
D3.5 Integrated Single Core Toolchain Prototype Year 8/2010 - 4/2012 Authors: Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu-Grosjean, Guillem Bernat, Benoit Triquet, Jaume Abella, Leonidas Kosmidis, Emery Berger, Elisa Turrini, Enrico Mezzetti, Andrea Baldovin, Luca Santinelli, Code Lo, Dorin Maxim, Mike Houston, Ian Broster, Mike Towers, Franck Wartel Barcelona Supercomputing Center, University of Padova, INRIA, Rapita Systems Ltd., Airbus |
|
D3.3: Non-Integrated Single-Core Tool-chain Prototype Components Year 7/2010 - 12/2011 Authors: Jaume Abella, Francisco J. Cazorla, Liliana Cucu-Grosjean, Michael Houston, Leonidas Kosmidis, Eduardo Quiñones, Tullio Vardanega Barcelona Supercomputing Center, University of Padova, INRIA, Rapita Systems Ltd. |
|
D5.3: Project Requirements and Success Criteria D1.1: Technical Specification: Platform D2.1: Technical Specification: Software Technology D3.1: Technical Specification: Probabilistic Timing Method Selection D4.1: Technical Specification: Avionics Application Porting D3.2: Baseline Integrated Tool-chain All these reports have been provided into a single document Year 2/2010 - 7/2010 Authors: Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu-Grosjean, Guillem Bernat, Benoit Triquet, Jaume Abella, Leonidas Kosmidis, Emery Berger, Elisa Turrini, Enrico Mezzetti, Andrea Baldovin, Luca Santinelli, Code Lo, Dorin Maxim, Mike Houston, Ian Broster, Mike Towers, Franck Wartel Barcelona Supercomputing Center, University of Padova, INRIA, Rapita Systems Ltd., Airbus |
MHAOTEUMemory Hierarchy Analysis and Optimization Tools for End UsersEsprit 4 RTD project number 24942 From 16-June-1999 until 30-June-2001 |
|
Report M2.D1: Extended Performance Analysis Year 1999 - 2000 Authors: Jaume Abella, Nerina Bermudo, Josep M. Codina, Carlos Ciuraneta, Christine Eisenbeis, Antonio González, Josep Llosa, Andry Randrianatoavina, François Thomasset, Sid Ahmed Ali Touati, Xavier Vera INRIA, Universidad Politécnica de Cataluña |
|
Report M2.D2: Extended Optimisation Techniques Year 1999 - 2000 Authors: Jaume Abella, Josep M. Codina, Carlos Ciuraneta, Min Dai, Christine Eisenbeis, Antonio González, Josep Llosa, Peter Knijnenburg, Michael O'Boyle, Sid Ahmed Ali Touati, Xavier Vera INRIA, Leiden University, Universidad Politécnica de Cataluña, University of Edinburgh |
|
Report M2.D3: Analysis of Application Codes Year 1999 - 2000 Authors: Jaume Abella, Josep M. Codina, Carlos Ciuraneta, Antonio González, Josep Llosa, Kathryn S. McKinley, Olivier Temam, Xavier Vera LRI Paris South, Universidad Politécnica de Cataluña, University of Massachussets |
|
Report M3.D1: Advanced Performance Analysis Year 2000 - 2001 Authors: Jaume Abella, Grigori Fursin, Antonio González, Josep Llosa, Michael O'Boyle, Abhishek Prabhat, Olivier Temam, Sid Ahmed Ali Touati, Xavier Vera, Gregory Watts INRIA, LRI Paris South, Universidad Politécnica de Cataluña, University of Edinburgh |
|
Report M3.D2: Guided Transformations Year 2000 - 2001 Authors: Jaume Abella, Cédric Bastoul, Jean-Luc Béchennec, Carlos Ciuraneta, Nathalie Drach, Christine Eisenbeis, Paul Freautier, Bjoern Franke, Grigori Fursin, Antonio González, Toru Kisku, Peter Knijnenburg, Josep Llosa, Michael O'Boyle, Julien Sébot, Xavier Vera INRIA, Leiden University, Universidad Politécnica de Cataluña, University of Edinburgh |