Joan-Manuel Parcerisa Professor Col·laborador     Phone: +34 934011653  Fax:     +34 934017055  Email:   jmanel  AT  ac DOT upc DOT edu   Department of Computer Architecture   Universitat Politècnica de Catalunya (UPC)   c. Jordi Girona 1-3, dptx. C6-116, Campus Nord  08034 Barcelona, Spain

Journals

• On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures
  Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González and José Duato
  IEEE Transactions on Parallel and Distributed Systems, 16(2):130-144, IEEE Computer Society, February 2005

• Improving Latency Tolerance of Multithreading through Decoupling
  Joan-Manuel Parcerisa and Antonio González.
  IEEE Transactions on Computers, 50 (10): 1084-1094, IEEE Computer Society, October 2001

• Dynamic Code Partitioning for Clustered Architectures
  Ramon Canal, Joan Manuel Parcerisa and Antonio González
  International Journal of Parallel Programming, 29 (1): 59-79, Kluwer Academic/Plenum Publishers, February 2001

Conferences

• Early Register Release for Out-of-Order Processors with Register Windows
  Eduardo Quiñones, Joan-Manuel Parcerisa and Antonio González
  2007 Int. Conf. on Parallel Architectures and Compilation Techniques (PACT-2007), pp. 225-234, September 2007

• Improving Branch Prediction and Predicated Execution in Out-of-Order Processors
  Eduardo Quiñones, Joan-Manuel Parcerisa and Antonio González
  13th. Int. Symp. on High-Performance Computer Architecture (HPCA-13), pp. 75-84, February 2007

• Selective Predicate Prediction for Out-of-Order Processors
  Eduardo Quiñones, Joan-Manuel Parcerisa and Antonio González
  2006 Int. Conf. on Supercomputing (ICS06), pp. 46-54, June 2006

• Memory Bank Predictors
  Stefan Bieschewski, Joan-Manuel Parcerisa and Antonio González
  2005 IEEE Int. Conf. on Computer Design (ICCD-2005), pp. 666-668, October 2005

• Efficient Interconnects for Clustered Microarchitectures
  Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González and José Duato
  2002 Int. Conf. on Parallel Architectures and Compilation Techniques (PACT-2002), pp. 291-300, September 2002

• Reducing Wire Delay Penalty through Value Prediction
  Joan-Manuel Parcerisa and Antonio González
  33rd. Annual IEEE/ACM Int. Symp. on Microarchitecture (MICRO-33), pp. 317-326, December 2000

• Dynamic Cluster Assignment Mechanisms
  Ramon Canal, Joan Manuel Parcerisa and Antonio González
  6th. Int. Symp. on High-Performance Computer Architecture (HPCA-6), pp. 133-142, January 2000

• A Cost-Effective Clustered Architecture
  Ramon Canal, Joan Manuel Parcerisa and Antonio González
  1999 Int. Conf. on Parallel Architectures and Compilation Techniques (PACT-99), pp. 160-168, October 1999

• The Synergy of Multithreading and Access/Execute Decoupling
  Joan-Manuel Parcerisa and Antonio González
  5th. Int. Symp. on High-Performance Computer Architecture (HPCA-5), pp. 59-63, January 1999

• The Latency Hiding Effectiveness of Decoupled Access/Execute Processors
  Joan-Manuel Parcerisa and Antonio González
  24th. Euromicro Conference, (EUROMICRO-98), pp 293-300, August 1998

• Eliminating Cache Conflict Misses Through XOR-Based Placement Functions
  Antonio González, Mateo Valero, Nigel Topham and Joan M. Parcerisa
  1997 Int. Conf. on Supercomputing (ICS-97), pp. 76-83, July 1997

PhD Thesis

• Design of Clustered Superscalar Microarchitectures
  Joan-Manuel Parcerisa
  PhD. Thesis at Universitat Politècnica de Catalunya, June 2004
  Technical Report UPC-DAC-2004-49, Computer Architecture Department (UPC)

I am currently advisor of two PhD. students:

• Stefan Bieschewski
• Eduardo Quiñones

I am currently responsible of the course:

• Computer Structure 1
  This course is part of the studies of Computer Science Engineering, in the Facultat d'Informàtica de Barcelona (english version)