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Marco A. Peña Personal Page  



I am lecturer (lector), currently teaching at the Technical University of Catalonia (UPC). I got my Bs. and MSc. Degrees in Computer Science in 1993 and 1995 respectively, from the Computer Science Faculty of Barcelona  at UPC. Since 1997, I'm working at the Computer Architecture Department where I got my PhD in Computer Science in 2003, with a thesis about the formal verification of timed systems. All my research has been carried out within the VLSI/CAD Group . My research interests include  logic synthesis and verification of asynchronous circuits, symbolic Petri net analysis, formal verification of timed systems, and several aspects related to the development of embedded systems.



Contact information

You can reach me at the following address:

Marco A. Peña
Departament d' Arquitectura de Computadors
Universitat Politècnica de Catalunya (UPC)
Escola Politècnica Superior de Castelldefels (EPSC)
Avinguda del Canal Olimpic, s.n.
08860 - Castelldefels, SPAIN

About this web-site:

These web pages are structured into four main parts:

  • In the Teaching area you will find information about the courses and subjects I have tought or I am currently teaching, teaching-related publications and presentations, and a list of final degree projects I have advised.
  • The Research area summarizes information about my theses, papers in conferences and research journals, research reports, etc.
  • The Publications area includes a list of publications in technical (not research) journals and the like.


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Last update: 12.20.2007
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