Year 2004

• .NET as a Platform for Embedded Systems
  E. Pastor, J. López and M.A. Peña,
  IV Jornadas de Computación Reconfigurable y Aplicaciones,  
  Barcelona, Spain, September 2004.

Year 2003

• TRANSYT: A tool for the verification of asynchornous consurrent systems
  E. Pastor, M.A. Peña and M. Solé,
  Correct Hardware Design and Verification Methods, 
  Lecture Notes in Computer Science, vol. 3576, pages. 424-428, Springer Verlag, 
  L'Aquila, Italy, October 2003.
   
• Efficient Hybrid Reachability Analysis for Asynchronous concurrent systems
  E. Pastor and M.A. Peña,
  Lecture Notes in Computer Science, vol. 2860, pages. 378-393, Springer Verlag, 
   
• Combining Simulation and Guided Traversal for the Verification of Concurrent Systems
  E. Pastor and M.A. Peña,
  Design, Automation and Test in Europe (DATE), pages 1158-1159, 
  Munich, Germany, March 2003.
   
• Relative Timing Based Verification of Concurrent Systems
  M.A. Peña,
  EDAA PhD. Forum, Design, Automation and Test in Europe (DATE), 
  Munich, Germany, March 2003.
  Click here for the abstract.

Year 2002

• A Case Study for the Verification of Complex Timed Circuits: IPCMOS
  M.A. Peña, J. Cortadella, E. Pastor and A. Smirnov,
  Design, Automation and Test in Europe (DATE), pages 44-51, 
  Paris, France, March 2002.
  Slides used in the conference.

• Formal Verification of a Complex Timed Circuit: IPCMOS
  M.A. Peña, J. Cortadella, E. Pastor and A. Smirnov,
  Asynchronous Circuit Design (ACiD)-WG/EXACT Workshop, 
  Munich, Germany, January 2002.
  Click here for the abstract.
  Slides used in the conference.

Year 2000

• Formal Verification of Safety Properties in Timed Circuits
  M.A. Peña, J. Cortadella, A. Kondratyev and E. Pastor,
  Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 2-11,
  Eilat, Israel, April 2000.
  Slides used in the conference.

• Formal Verification of Safety Properties in Timed Transition Systems
  M. A. Peña, J. Cortadella, A. Kondratyev and E. Pastor
  Asynchronous Circuit Design (ACiD)-WG/EXACT Workshop,
  Grenoble, France, January 2000.
  Click here for the abstract.

Year 1999

• A Symbolic Technique for the Efficient ATPG of Speed-Independent Circuits
  M. A. Peña, E. Pastor and J. Cortadella,
  XIV Design of Circuits and Integrated Systems Conference (DCIS), pages 295-300,
  Palma de Mallorca, Spain, November 1999.
  Slides used in the conference.

• Structural Methods to Improve the Symbolic Analysis of Petri Nets
  E. Pastor, J. Cortadella and M. A. Peña,
  20th International Conference on Application and Theory of Petri Nets (ICATPN),
  Lecture Notes in Computer Science, vol. 1639, pages. 26-45, Springer Verlag, 
  Williamsburg, Virginia, USA, June 1999.

Year 1997

• Synthesis of Speed-Independent Circuits from STG-unfolding Segment
  A. Semenov, A. Yakovlev, E. Pastor, M. A. Peña and J.  Cortadella,
  34th Design Automation Conference (DAC), pages 16-21,
  Anaheim, California, USA, June 1997.

• Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits
  O. Roig, J. Cortadella, M.A. Peña and E. Pastor,
  34th Design Automation Conference (DAC), pages 620-625,
  Anaheim, California, USA, June 1997.

• Partial Order Based Approach to Synthesis of Speed-Independent Circuits
  A. Semenov, A. Yakovlev, E. Pastor, M. A. Peña, J. Cortadella and L. Lavagno,
  Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 254-265,
  Eindhoven, The Netherlands, April 1997.

Year 1996

• Synthesis of Speed-Independent Circuits from STG-Unfolding Segment
  A. Semenov, A. Yakovlev, E. Pastor, M. A. Peña and J. Cortadella,
  Asynchronous Circuit Design (ACiD)-WG/EXACT Workshop,
  Groningen, The Netherlands, September 1996.

• Flujo de diseño asíncrono con la biblioteca DCVSL_LIB para ES2 ECPD10
  L. Sintes, J. Escudero, M. A. Peña, O. Roig, J. Cortadella and J. Carrabina,
  Segundo Congreso sobre Tecnologías Aplicadas a la Enseñanza de la Electrónica (TAEE), pages 161-166,
  Sevilla, Spain, September 1996.
  

• Combining Process Algebras and Petri Nets for the Specification and Synthesis of Asynchronous Circuits
  M.A. Peña and J. Cortadella,
  Second International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 222-232,
  Aizu-Wakamatsu, Japan, March 1996.
  Slides used in the conference.

Year 1995

• Programación VLSI y síntesis de circuitos asíncronos mediante composición de redes de Petri
  M.A. Peña and J. Cortadella
  X Congreso de Diseño de Circuitos Integrados y Sistemas (DCIS), pages 65-70,
  Zaragoza, Spain, November 1995.
  Slides used in the conference.