| [ToC'08] |
C. Martinez, M. Moreto, R. Beivide, E. Gabidulin and E. Stafford. Modeling Toroidal Networks with the Gaussian Integers. IEEE Transactions on Computers, vol. 57, no. 8, August 2008. |
| [Micro'08] |
K. J. Nesbit, M. Moreto, F. J. Cazorla, A. Ramirez, M. Valero, and
J. E. Smith. Virtual Private Machines: Hardware/Software Interactions in the Multicore
Era. IEEE Micro, special issue on Interaction of Computer Architecture and Operating
System in the Manycore Era, vol. 38, no. 3, May/June 2008. |
| [ToHiPEAC'08] |
M. Moreto, F. J. Cazorla, A. Ramirez and M. Valero. Dynamic Cache Partitioning based on the MLP of Cache Misses. Transactions on High Performance Embedded Architectures and Compilers. vol. 3, no. 1, March 2008. |
| [CAL'07] |
M. Moretó, F. J. Cazorla, A. Ramirez and M. Valero. Explaining Dynamic Cache
Partitioning Speed Ups. IEEE Computer Architecture Letters, vol. 6, no. 1, March
2007. |
| [IJPP'06] |
C. Martínez, E. Vallejo, R. Beivide, C. Izu and M. Moretó. “Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors”. International Journal of Parallel Programming, Vol. 33, No. 3, June 2006. |
| [CEC'08] |
P. A. Castillo, J. J. Merelo, M. Moreto, F. J. Cazorla, M. Valero, A. M. Mora, J. L. J. Laredo, and S.A. McKee. Evolutionary system for prediction and optimization of hardware architecture performance. IEEE Congress on Evolutionary Computation (CEC). Hong Kong. June 2008. |
| [HiPEAC'08] |
M. Moreto, F. J. Cazorla, A. Ramirez and M. Valero. MLP-aware dynamic cache partitioning. International Conference on High Performance Embedded Architectures and Compilers (Hipeac). Goteborg, Sweden, January 2008. |
| [SAMOS'07] |
M. Moreto, F. J. Cazorla, A. Ramirez and M. Valero. Online Prediction of Applications Cache Utility. International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS). July 2007. |
| [IPDPS'07] |
J. Cámara, M. Moretó, E. Vallejo, R. Beivide, C. Martínez, J. Miguel-Alonso and J. Navaridas. “Mixed-radix Twisted Torus Interconnection Networks”. IEEE International Parallel and Distributed Processing Symposium (IPDPS). Long beach, USA, March 2007. |
| [ISIT'06] |
C. Martínez, M. Moretó, R. Beivide and E. Gabidulin. “A Generalization of Perfect Lee Codes over Gaussian Integers”. IEEE International Symposium on Information Theory. Seattle, USA. July 2006. |
| [EVOHot'08] |
P. A. Castillo, A. M. Mora, J. J. Merelo, J. L. J. Laredo, M. Moreto, F. J. Cazorla, M. Valero, and S.A. McKee. Architecture performance prediction using evolutionary artificial neural networks. European Workshop on Hardware Optimization Techniques (EVOHot). Napoli, Italy. March 2008. |
| [PACT'07] |
M. Moretó, F. J. Cazorla, A. Ramirez and M. Valero. MLP-aware dynamic cache partitioning. PACT 2007, Poster Abstracts. International Conference on Parallel
Architectures and Compilation Techniques (PACT). Brasov, September 2007. |
| [ACACES'06] |
M. Moretó, A. Ramírez and M. Valero. “Reducing Simulation Time ”. ACACES 2006. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 24-28, pp. 233-236. Academic Press, ISBN 90 382 0981 9. |
| [ACACES'05] |
M. Moretó, C. Martínez, R. Beivide, E. Vallejo and M. Valero. “Hierarchical Gaussian Topologies”. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. L'Aquila, July 25-29, pp. 211-214. Academic Press, ISBN 90 382 0802 2. |
