About me

I am a Full Professor (Catedràtic d'Universitat) and former Vice Dean of Postgraduate Studies at the Facultat d'Informàtica de Barcelona (Barcelona School of Informatics), part of the Universitat Politècnica de Catalunya – BarcelonaTech (UPC). Since September 2025, I have been teaching at the Manresa School of Engineering (EPSEM) of UPC. Previously, I was a member of the Computer Architecture Department, in the VirtuOS (Virtualization and Operating Systems) group.

I received my BSc, MSc and PhD (2004) degrees from UPC. My thesis was supervised by Antonio González (UPC) and James E. Smith (University of Wisconsin–Madison). I happily spent a sabbatical at Harvard University during the 2006–2007 academic year, and another at the University of Cyprus during 2019–2020. I also gained industry experience at Sun Microsystems (USA).

Projects

• VITAMIN-V: Virtual Environment and Tool-Boxing for Trustworthy Development of RISC-V based Cloud Services (EU Horizon Europe, 2023–2025). Role: Coordinator (PI).
• WISE4: Made-in-Europe, Secure, Resilient, Efficient Open-Source Computing Infrastructure for Web 4.0 (EU Horizon Europe, 2026–2029). Role: Scientific coordinator at UPC.
• TURANDOT: Tuning RISC-V to Automotive Needs & Different Other Themes (Chips JU, 2026–2030). Role: Scientific coordinator at UPC.
• ISOLDE: High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems (Chips JU, 2023–2026). Role: Task leader.
• EUMaster4HPC: European Master for High-Performance Computing (EU Horizon 2020, 2022–2025). Role: Work package leader.

Current lectures

• Introduction to Digital Systems (BSc in ICT Systems Engineering)
• Computer Architecture (BSc in ICT Systems Engineering)
• Malware Detection (MSc in Machine Learning and Cybersecurity)
• Introduction to High-Performance Computing (MSc in Machine Learning and Cybersecurity)

Past lectures

• Nanotechnology Circuit Design (MIRI Master)
• Processor Design (MIRI Master)
• VLSI Design (BSc in Computer Engineering)
• Disseny i Tecnologia de Computadors (DTC) (Computer Design and Technology)
• Disseny de Microprocessadors (DM) (Microprocessor Design), BSc and MSc in Computer Engineering, 2004 curriculum
• Computer Architecture (MTI Master)
• Processor Architecture (MIRI Master)
• Introducció als Computadors (IC) (Introduction to Computers)

Honors and awards

• IEEE IOLTS Conference Award for significant and sustained contributions to the symposium over multiple years, 2024.
• HiPEAC Paper Award for the publication “MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment” in ISCA-44, 2017.
• IEEE Senior Member (2016) and ACM Member.
• Best Paper Nominee for the paper “iRMW: A Low-Cost Technique to Reduce NBTI-Dependent Parametric Failures in L1 Caches” in ICCD-32, 2014.
• Recognition for Excellence in Teaching (2008–2012, evaluated every five years). Mèrits de docència d'especial qualitat (quinquenni 2008–2012). UPC and AQU Catalunya, 2013.
• Best Paper Award for the paper “Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm” in DCIS 2012.
• Recognition for Excellence in Teaching (2003–2007, evaluated every five years). Mèrits de docència d'especial qualitat (quinquenni 2003–2007). UPC and AQU Catalunya, 2010.
• HiPEAC Paper Award for the publication “A hybrid eDRAM/SRAM macrocell to implement first-level data caches” in MICRO-42, 2010.
• First prize in the 6th Duran Farell Award for technology and research in Spain (UPC and Gas Natural), as a member of the research team of the project “Efficient processor design through clustering” (UPC press room) (UPC Informacions magazine, p. 10), 2008.
• Certificate of Appreciation in recognition of the inclusion of “Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability” in the Jan/Feb 2008 IEEE Micro Top Picks special issue on the most industry-relevant and significant computer architecture papers of 2007 (certificate), 2008.
• Fulbright Award, Commission for Cultural, Educational and Scientific Exchange between the United States of America and Spain, and the Generalitat de Catalunya, 2006 (certificate).
• First prize in the Epson Foundation Rosina Ribalta Award for the best thesis project in the area of Information Technologies in Spain and Portugal (awards web page) (thesis project) (thesis project presentation) (article in Teraflop), 2001.
• IBM Faculty Award for my work on value compression, 2000.
• Best Student Paper Award for the paper “Dynamic Cluster Assignment Mechanisms” in HPCA-6, 2000.

Professional service

Associate editor

• IEEE Transactions on Computers (TC)
• Journal of Parallel and Distributed Computing (JPDC)
• ACM Transactions on Architecture and Code Optimization (TACO)

Conference organization

• General Co-Chair, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), Barcelona, 2025
• Financial Chair, ACM ASPLOS 2027
• Industrial Co-Chair, IEEE European Test Symposium (ETS), 2022

Program committee member

• ISCA (since 2017)
• HPCA (since 2018)
• MICRO (since 2020)

Networks and community

• EUCloudEdgeIoT: member of the Cybersecurity and AI for cloud-edge workgroup
• HiPEAC: member
• RISC-V International: Security Horizontal Committee, Datacenter Special Interest Group, and Academic and Training Special Interest Group
• OpenHW Group: CORE-V Cores Task Group and Software Task Group

Curriculum vitae

• Here you can find a brief CV.

Media contributions

• TV3 (February 7th, 2026) Impact of AI demand on consumer electronic prices
• RNE (May 12th, 2024)

Manresa, October 2026