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Biography

Adrià Armejach is a Juan de la Cierva Fellow at the Computer Architecture Departament (DAC) at the Universitat Politècnica de Catalunya-Barcelona Tech (UPC), where he teaches Computer Organization and works within the High Performance Computing (CAP) research group.

His primary research interests include high performance computer architectures, parallel architectures, hardware-software co-design, accelerators for genomics and machine learning applications, simulation methodologies and performance analysis.

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Teaching

• EC Spring 2022 Computer Organization
• EC Spring 2020 Computer Organization
• SO Fall 2018 Operating Systems
• SO Fall 2017 Operating Systems
• EC Spring 2017 Computer Organization

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Advising

Current

• Engineer Francesc Martinez
• Postdoc Milan Radulovic
• Postdoc Alireza Monemi
• PhD Student Marco Siracusa (Started November 2021)
• PhD Student Rubén Langarita (Started October 2021)
• PhD Student Alexandre de Limas Santana (Started May 2021)
• PhD Student Guillem López (Started March 2021)
• PhD Student John Osorio (Started February 2019)
• MSc Student Víctor Soria (Started September 2019)

Former (first employment)

• PhD 2021 Adrián Barredo (Huawei, Cambridge, UK)
• MSc 2021 Rubén Langarita (BSC, Spain)
• MSc 2020 Guillem López (BSC, Spain)
• BSc 2019 Víctor Soria (BSC, Spain)
• Visiting Student 2015 Naveed Ul Mustafa (University of Central Florida, USA)

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Publications

h-index: 10   Citations: 408   Erdös #: 3   ORCID   Google Scholar   DBLP

Peer-reviewed Conferences

• ICMLA'21 Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training. John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, and Marc Casas. In IEEE 2021 International Conference on Machine Learning and Applications (ICMLA), 2021.
• ICPP'21 gem5+RTL: A Framework to Enable RTL Models Inside a Full-System Simulator. Guillem Lopez-Paradis, Adrià Armejach, and Miquel Moretó. In International Conference on Parallel Processing (ICPP), 2021.
• ICS'21 PLANAR: a programmable accelerator for near-memory data rearrangement. Adrián Barredo, Adrià Armejach, Jonathan C. Beard, and Miquel Moretó. In ICS ’21: 2021 International Conference on Supercomputing, Virtual Event, USA, June 14-17, 2021, pages 164–176, 2021.
• DATE'21 Mont-Blanc 2020: Towards European, Scalable, and Power Efficient HPC Processors. Adrià Armejach, Bine Brank, Jordi Cortina, Francoise Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem Lopez-Paradis, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, and Said Derradji. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, DATE, 2021.
• ICMLA'20 Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors. John Osorio Ríos, Adrià Armejach, Gulrukh Khattak, Eric Petit, Sofia Vallecorsa, and Marc Casas. In Proceedings of the 19th IEEE International Conference on Machine Learning and Applications, ICMLA 2020, Miami, FL, USA, December 14-17, 2020, pages 49–56, 2020.
• IPDPS'19 Design Space Exploration of Next-Generation HPC Machines. Constantino Gómez, Francesc Martínez, Adrià Armejach, Miquel Moretó, Filippo Mantovani, and Marc Casas. In Proceedings of the 2019 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2019, Rio de Janeiro, Brazil, May 20-24, 2019, pages 54–65, 2019.
• PACT'18 Stencil codes on a vector length agnostic architecture. Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, and Miquel Moretó. In Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, PACT 2018, Limassol, Cyprus, November 01-04, 2018, pages 13:1–13:12, 2018.
• SAMOS'16 Implications of non-volatile memory as primary storage for database management systems. Naveed Ul Mustafa, Adrià Armejach, ̈Ozcan ̈Ozturk, Adri ́an Cristal, and Osman S. Unsal. In International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016, pages 164–171, 2016.
• SC'16 MUSA: A multi-level simulation approach for next-generation HPC machines. Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, and Miquel Moretó. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2016, Salt Lake City, UT, USA, November 13-18, 2016, pages 526–537, 2016.
• SBAC-PAD'15 Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches. Adrià Armejach, Adrián Cristal, and Osman S. Unsal. In 27th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2015, Florianópolis, Brazil, October 17-21, 2015, pages 65–73, 2015.
• FPL'14 Oriol Arcas-Abella, Geoffrey Ndu, Nehir Sönmez, Mohsen Ghasempour, Adrià Armejach, Javier Navaridas, Wei Song, John Mawer, Adrián Cristal, and Mikel Luján. In Proceedings of the 24th International Conference on Field Programmable Logic and Applications, FPL, September 2014.
• HiPC'13 HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, and Tim Harris. In Proceedings of the 20th International Conference on High Performance Computing, HiPC ’13, December 2013.
• PACT'12 Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, and Per Stenstrom. Transactional Prefetching: Narrowing the Window of Contention in Hardware Transactional Memory. In Proceedings of the 21th International Conference on Parallel Architectures and Compilation Techniques, PACT, September 2012.
• NORCHIP'12 Novel SRAM bias control circuits for a low power L1 data cache. Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, and Mateo Valero. In Proceedings of the 30th Norchip Conference, NORCHIP’12, November 2012.
• PACT'11 Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. Adrià Armejach, Azam Seyedi, Rubén Titos, Ibrahim Hur, Osman S. Unsal, Adrián Cristal, and Mateo Valero. In Proceedings of the 20th International Conference on Parallel Architectures and Compilation Techniques, PACT, October 2011.
• GLSVLSI'11 Best paper Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency. Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, and Mateo Valero. In Proceedings of the 21th Symposium on Great Lakes Symposium on VLSI, GLSVLSI ’11, May 2011.
• MICRO'09 EazyHTM: eager-lazy hardware transactional memory. Sasa Tomić, Cristian Perfumo, Chinmay Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, and Mateo Valero. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO ’09, December 2009.

Peer-reviewed Journals

• TCBB'21 Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps. Rubén Langarita, Adrià Armejach, Javier Setoain, Pablo E. Ibañez Marín, Jesús Alastruey-Benede, and Miquel Moretó. IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2021.
• JoS'21 On the use of many-core Marvell ThunderX2 processor for HPC workloads. Víctor Soria Pardos, Adrià Armejach, Darío Suárez, and Miquel Moretó. J. Supercomput., 77(4):3315–3338, 2021.
• JoS'20 Using Arm's scalable vector extension on stencil codes. Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, and Miquel Moretó. J. Supercomput., 76(3):2039–2062, 2020.
• JoS'19 Design trade-offs for emerging HPC processors based on mobile market technology. Adrià Armejach, Marc Casas, and Miquel Moretó. J. Supercomput., 75(9):5717–5740, 2019.
• CiSE'16 Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory. Oriol Arcas-Abella, Adrià Armejach, Timothy Hayes, Gorker Alp Malazgirt, Oscar Palomar, Behzad Salami, and Nehir Sönmez. Computing in Science and Engineering, 18(1):80–87, 2016.
• TACO'13 Techniques to Improve Performance in Requester-wins Hardware Transactional Memory. Adrià Armejach, Ruben Titos-Gil, Anurag Negi, Osman S. Unsal, and Adrián Cristal. ACM Transactions on Architecture and Code Optimization (TACO), 10(4):42:1–42:25, December 2013.
• Integration'12 Circuit design of a dual-versioning L1 data cache. Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, and Mateo Valero. Integration, 45(3):237–245, 2012.