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Enric Pastor Personal Page  



I'm full time associate professor, currently teaching at the Universitat Politècnica de Catalunya. I've got my PhD in computer science from the "Universitat Politècnica de Catalunya" on April 1996. Since 1991, I'm working at the Computer Architecture Department (Departament d'Arquitectura de Computadors). Currently, all my research is been carried out in the VLSI CAD group. My research interests are logic synthesis and verification of asynchronous circuits, symbollic Petri net analysis and timed verification.

You can see a picture of me here.

Contact information

You can reach me at the following address:

Enric Pastor
Department of Computer Architecture
Universitat Politecnica de Catalunya
Escola Politècnica Superior de Castelldefels
Avinguda del Canal Olimpic, s.n.
08860 - Castelldefels, SPAIN
E-mail: enric@ac.upc.es
Phone : +34-93-4137103
Fax : +34-93-4017055
WWW : http://www.ac.upc.es

Undergraduate Courses

I currently teach the following undergraduate courses:

I also offer final year projects for both studies. Here you have a list of the courses I may supervise.

  • Information on final year projects [FIB] [EUBL].

Graduate Courses

I currently teach the following graduate courses in the graduate program Arquitectura y Tecnologia de Computadores:

  • Evaluating the impact of technology on micro-architecture
  • Diseno Basico VLSI (DBVLSI).


La asignatura pretende que los estudiantes puedan evaluar y sistemas


My thesis was titled "Structural Methods for the Synthesis of Asynchronous Circuits from Signal Transition Graphs". This work proposes a efficient methodology for the synthesis of speed-independent circuits based on the analysis of the structure of the Signal Transition Graph rather than the generation of its corresponding State Graph. This approximation overcomes the state explosion problem, and allows the synthesis of STG specifications with more than 1x10^27 states.

Index of the Thesis
Preface of the Thesis
Slides of the defense


Some of the technical reports and papers related to my current and previous research areas of interest: synthesis and verification of asynchronous circuits, symbollic analysis of Petri Nets and timed verification.





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Last update: 15 de january del 2002
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