Power Trace Analyzer


The tutorial will cover the main issues for building power models based on hardware counters. Initially we describe the basic options to generate a platform where to build a model (device for getting actual power measurements, sampling the device, getting the measurements, reading the counters) (30 min).

Second, we describe how to breakdown a multi-core architecture in components from where to obtain power contributions on the overall power consumption (30 min).

The tutorial describes the set of counters commonly available in last generation multi-core architectures, and which ones better describe the activity of each architectural component (45 min).

The tutorial describes how to linearly correlate the activity in each component with actual power. We describe a basic algorithm that uses stochastic methods (linear regression) to build power models (45 min). Finally, the tutorial describes how to validate a power model in terms of accuracy and responsiveness (30 min).

Each step of the tutorial is applied to a multi-core architecture.

Expected duration: 3 hours

Intended audience and assumed background:

The tutorial is addressed to computer scientist, with specific interest on performance modeling for computer architectures. The tutorial assumes basic knowledge on hardware counters and their variety.


We expect everyone attending the tutorial bring his own laptop. Slides will be distributed electronically.



Power consumption estimation for different power models and percentage of error for bwaves application from the SPEC2006 benchmark suite. PoTra allows for a time view of power analyses and estimation. PoTra includes support for power phases detection, what enables the validation of power models and their responsiveness to power phases.

Breakdown of component activity (events per cycle) and overall power consumption for bwaves application in the SPEC2006 benchmark suite.