Francisco J. Cazorla's Home Page

Below a list of the projects in which I have been involved. In some of them as coordinator.

		(Coordinated)(2018-2023) SuPerCom is a Consolidator Grant by the European Research Council. SuPerCom addresses the challenge of providing high and sustainable performance (hsperf) covering the highest-ever computation performance needs of critical software with strong guarantees on sustainability for safe operation. This will be tackled for future mixed-criticality embedded computers comprising high-performance hardware with unprecedented complexity levels. To reach its goals, SuPerCom proposes a radical new approach by combining performance analysis, hardware design, and statistical and machine learning analysis.

		(Coordinated)(2020-2021) MASTECS (Multicore Analysis Service and Tools for Embedded Critical Systems) will bring to the market innovative and exploitable technology for multicore processor timing analysis (MTA). It will be used by critical embedded software industries (focusing on automotive and avionics) to support advanced software functions (such as autonomous driving) which are competitive factors in every new product. MASTECS will enable these industries to exploit increased computing performance from multicore platforms allowing new functionally-rich critical and performance-demanding software, leading to reduced fatalities in the road, safer and cheaper air travel and reducing CO2 profile of planes and cars.

		(Coordinated)(2018-2019) The AMTA (Avionics Multicore Timing Analysis) project aims to investigate and evaluate the interaction/contention among different tasks deployed in a multicore system to derive realistic WCET estimates and improve timing-related safety aspects. This will also ease the certification process by enabling optimal partitioning choices and enhanced scheduling algorithms. Modeling the interactions among tasks accurately gives valuable information to the scheduling process while enabling a tighter calculation for the WCET.

		(Coordinated)(2013-2016) PROXIMA is a Integrated Project (IP) of the Seventh framework programme for research and technological development (FP7). The PROXIMA project provides industry ready software timing analysis using probabilistic analysis for many-core and multi-core critical real-time embedded systems and will enable cost-effective verification of software timing analysis including worst case execution time.

		(2013-2016) The project SAFURE targets the design of cyber-physical systems by implementing a methodology that ensures safety and security "by construction". This methodology is enabled by a framework developed to extend system capabilities so as to control the concurrent effects of security threats on the system behaviour. The current approach for security on safety-critical embedded systems is generally to keep subsystems separated, but this approach is now being challenged by technological evolution towards openness, increased communications and use of multi-core architectures..

		(2015-2016) In close collaboration with PROXIMA, a European Space Agency (ESA) project "PROARTIS for Space" focuses on applying some of the PROARTIS/PROXIMA principles to space applications. Partners Astrium, BSC, Rapita, UPD and Gaisler will perform a case study on future Leon processors.

		(2014-2015) Emulator of Future NGMP Multicore HAIR presents a hypervisor emulator capable of emulating future multicore processors, NGMP in concrete a SPARC V8 quad-core processor, based on the LEON4 and using Time and Space partitioning (TSP) technology based AIR hypervisor. HAIR therefore obtains the best benefits of multicore and TSP, being representative/accurate by emulating the behaviour of the NGMP in terms of timing and functionality running on ESOC EMU 2.0 processor emulator; and also being performant by compiling the embedded application, along with AIR hypervisor and RTEMS BSP natively on the host workstation..

		(2011-2014) The motivation for the parMERASA project was the industry's demands for new functionality and higher levels of performance of embedded hard real-time systems. The parMERASA project developed a many-core processor architecture that provides a predictable timing behaviour, a suitable system-level software, software design guidelines for parallelising hard real-time applications, and tools for estimating and verifying the timing behaviour of such parallel applications..

		(Coordinated)(2010-2013) The aim of the PROARTIS project is to define new hardware and software architecture paradigms that, by design, exhibit a timing behaviour that can be effectively analysed with probabilistic techniques. The hypothesis of the PROARTIS project is that new advanced hardware features can be used and analysed effectively in embedded real-time systems when designs move towards more truly randomized behaviour which probabilistically reduces the risk of temporal pathological cases to quantifiably negligible levels. This approach enables probabilistic timing analysis techniques that can be used effectively in the verification of Critical Real-Time Embedded Systems.

		(2007-2010) The MERASA project focused on developing multi-core processor designs (from 2 to 16 cores) for hard real-time embedded systems hand in hand with timing analysis techniques and tools to guarantee the analysability and predictability regarding timing of every single feature provided by the processor. Design exploration activities were performed in conjunction with the timing analysis tools. The project addressed both static WCET analysis tools (the OTAWA toolset) as well as hybrid measurement-based tools (RapiTime) and their interoperability. It also developed system-level software with predictable timing performance.

		(Coordinated)(2007-2009) SoW on POWER5. In this project IBM and BSC intend to pursue a Research Collaboration to enable BSC to analyse, understand and evaluate the behaviour of SMT/CMP processor architectures, including but not limited to IBM's POWER5 processor. In particular, we analysed the interaction between the operating system and the IBM POWER5 processor; (2) we understand the effect of the IBM POWER5 hardware prioritization on performance; (3) we understand the SMT/CMP behaviour characteristics of workloads frequently executed in the BSC; and (4) we explore the design space of current and future SMT/CMP architectures.

		(Coordinated)(2007-2009) Real-time CMT architectures. In this project BSC and Sun microsystems Inc. collaborate in the area of Chip Multithreading (CMT) systems. As CMT systems we use boards based on the UltraSPARC T1 and T2 processors. In particular the project focuses on (1) Task scheduling of low-layer network-type of applications, such as IP Forwarding and (2) Analyzing the virtualization capabilities on the UltraSPARC T1 and T2 processors.

		(Coordinated)(2011-2013) Multicore OS benchmark. This activity targeted measuring multicore performance of the multicore LEON4 NGMP architecture and its timing analysability properties. A CCN extended the project to perform a similar evaluation to a LEON3-based GR712RC board. In this project, we developed a methodology for measuring multicore performance and to upper-bound inter-task interference. As a part of the methodology we developed specialized pieces of software called resource stressing kernels (RSK). RSK aim at creating interference in hardware target shared resource like the cache or the memory controller. The RSK methodology allows upper-bounding the impact on tasks execution time of multicore contention. The results obtained in this activity allowed the publication of the paper “Assessing the Suitability of the NGMP Multi-core Processor in the Space Domain” (EMSOFT 2012).

		(Coordinated)(2014-2015) Multi-core Architectures – Cache Structure optimization for better RT performance In this project we performe a literature review to gain knowledge on the implemented performance monitoring counters (PMC) in different architectures analysed. The review aimed at determining which PMC could be useful to analyse real-time behaviour -- instead of average-case application behaviour. The result of this work was a PMC taxonomy. A set of PMCs are proposed to be implemented in the NGMP to build a CPI stack where inter-core interference is measured for each shared resource. The results obtained in this activity allowed the publication of the paper “Contention-Aware Performance Monitoring Counter Support for Real-Time MPSoCs” (in the 11th IEEE International Symposium on Industrial Embedded Systems (SIES).

		(Coordinated)(2015-2016) Analysis of the suitability of implementing the eviction frequency limitation technique in the NGMP. In this project we analyse the feasibility of the implementation of the EFL mechanism in a LEON multicore architecture at FPGA level. EFL allows controlling how tasks affect each others' performance in cache by controlling their frequency of eviction in cache. For more information about EFL plese refer to "Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems", Design Automation Conference (DAC) 2014.