Home Publications Projects Reviewer Alumni HPES Awards Spin-off Personal

2025

Conferences

RTSS			David Fonts, Diego Palacios, Sergi Vilardell, Axel Brando, Isabel Serra, Enrico Mezzetti, Jaume Abella and Francisco J Cazorla . EMR: Removing Multicollinear Event Monitors to Improve Timing Modelling of Real-Time Systems. In 46th IEEE Real-Time Systems Symposium (RTSS). Dec 2025. Boston (MA), USA.
DSD			Jeremy Jens Giesen León, Ibai Irigoyen Ceberio, Enrico Mezzetti, Jaume Abella Ferrer, and Francisco J. Cazorla Impact of Contention-Aware Placement in Heterogeneous Edge Devices. In Proceedings of the 31st Euromicro DSD (Digital System Design)/SEAA (Software Engineering and Advanced Applications) conference. Salerno, Italy. September 2025
ECRTS			Blau Manau, Sergi Vilardell, Isabel Serra, Eenrico Mezzetti, Jaume Abella, and Francisco J Cazorla. Detecting Low-Density Mixtures in High-Quantile Tails for pWCET Estimation. In Proceedings of the 37th Euromicro Conference on Real-Time Systems (ECRTS 2025). Brussels, Belgium. July 2025.
ACM SAC			Sergi Vilardel, Francesco Rossi, Gabriele Giordana, Isabel Serra, Enrico Mezzetti, Jaume Abella, and Francisco J Cazorla Probabilistic Timing Estimates in Scenarios Under Testing Constraints. In The 40th ACM/SIGAPP Symposium On Applied Computing (SAC)Catania, Italy. March 2025
ACM SAC			Roger Pujol, Jaume Abella, Mohamed Hassan, FJ Cazorla. On the Time Predictability of AXI4. In The 40th ACM/SIGAPP Symposium On Applied Computing (SAC)Catania, Italy. March 2025

Journals

Elsevier JSA			Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Jaume Abella, Francisco J. Cazorla. Hardware support for contention tracking in CPU and GPU last-level cache. In Elsevier Journal of Systems Architecture (JSA). October 2025.
ACM DAES			Miguel Alcon, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla. Supporting Timing-related Metrics for Autonomous Driving Frameworks in CyberRT. In ACM Transactions on Design Automation of Electronic Systems. August 2025
IEEE ESL			Jaume Barrera, Leonidas Kosmidis, Jaume Abella, Francisco J Cazorla Assessing the use of NVIDIA Multi-Instance GPU in the Automotive Domain. In IEEE Embedded Systems Letters. April 2025

2024

Conferences

DSD			Roger Pujol, Sergi Vilardell, Enrico Mezzetti, Mohamed Hassan, Jaume Abella, Francisco J Cazorla. Event Monitor Validation in High-Integrity Systems. In 27th Euromicro DSD (Digital System Design)/SEAA (Software Engineering and Advanced Applications) conference. Paris (France), August 2024
DSD			Jeremy Giesen, Enrico Mezzetti, Jaume Abella, Francisco J Cazorla. TAP: Task-Aware Profiling on Integrated Systems. In 27th Euromicro DSD (Digital System Design)/SEAA (Software Engineering and Advanced Applications) conference. Paris (France), August 2024
DSD			Alejandro Serrano-Cases, Enrico Mezzetti, Jaume Abella, Francisco J Cazorla. Achieving Flexible Performance Isolation on the AMD Xilinx Zynq UltraScale+. In 27th Euromicro DSD (Digital System Design)/SEAA (Software Engineering and Advanced Applications) conference. Paris (France), August 2024
ACM SAC			Javier Barrera, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J Cazorla. Increasing Testing Robustness of GPU Software in Embedded Critical Systems. In 39th ACM/SIGAPP Symposium On Applied Computing (SAC 2024). Avila (Spain), April 2024
IEEE IOLTS			Adrià Aldomà, Axel Brando, Francisco J Cazorla, Jaume Abella. Safety-Relevant AI-Based System Robustification with Neural Network Ensembles. In 30th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS). Rennes (France), August 2024

Journals

ACM CSUR			Jon Perez-Cerrolaza, Jaume Abella, Markus Borg, Carlo Donzella, Jesús Cerquides, Francisco J Cazorla, Cristofer Englund, Markus Tauber, George Nikolakopoulos, Jose Luis Flores. Artificial Intelligence for Safety-Critical Systems in Industrial and Transportation Domains: A Survey. In ACM Computing Surveys (CSUR). Vol 56, No 7
IEEE ACCESS			Alejandro J Calderón, Leonidas Kosmidis, Carlos-F Nicolás, Francisco J Cazorla. XeroZerox: Analysis and Optimization of GPU Memory Management for High-Integrity Autonomous Systems. In IEEE Access

2023

Conferences

RTSS			Asier Fernandez-De-Lecea, Mohamed Hassan, Enrico Mezzetti, Jaume Abella, and Francisco J Cazorla . Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems. In 44th IEEE Real-Time Systems Symposium (RTSS). Dec 2023, Taipei, Taiwan.
ECRTS			Sergio Garcia-Esteban, Alejandro Serrano-Cases, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla. Quasi Isolation QoS Setups to Control MPSoC Contention in Integrated Software Architectures . In Proceedings of the 34th Euromicro Conference on Real-Time Systems (ECRTS 2023). Vienna, Austria. July 2023.
ETS			Fabio Pavanello, Cedric Marchand, Ian O’Connor, Régis Orobtchouk, Fabien Mandorlo, Xavier Letartre, Sebastien Cueff, Elena Ioana Vatajelu, Giorgio Di Natale, Benot Cluzel, Aurelien Coillet, Benoit Charbonnier, Pierre Noé, Frantisek Kavan, Martin Zoldak, Michal Szaj, Peter Bienstman, Thomas Van Vaerenbergh, Ulrich Ruhrmair, Paulo Flores, Luis Guerra e Silva, Ricardo Chaves, Luis-Miguel Silveira, Mariano Ceccato, Dimitris Gizopoulos, George Papadimitriou, Vasileios Karakostas, Axel Brando, Francisco J. Cazorla, Ramon Canal, Pau Closas, Adriá Gusi-Amigó, Paolo Crovetti, Alessio Carpegna, Tzamn Melendez Carmona, Stefano Di Carlo, and Alessandro Savino. NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS In 2023 IEEE European Test Symposium (ETS 2023). Venezia (Italy), May 2023
DATE			Jaume Abella, Jon Perez, Cristofer Englund, Bahram Zonooz, Gabriele Giordana, Carlo Donzella, Francisco J. Cazorla, Enrico Mezzetti, Isabel Serra, Axel Brando, Irune Agirre, Fernando Eizaguirre, Thanh Hai Bui, Elahe Arani, Fahad Sarfraz, Ajay Balasubramaniam, Ahmed Badar, Ilaria Bloise, Lorenzo Feruglio, Ilaria Cinelli, Davide Brighenti, Davide Cunial. SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AI In 26th Design, Automation and Test in Europe Conference (DATE 2023). Antwerp (Belgium), April 2023
ACM SAC			Jeremy J. Giesen, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla. ASCOM: Affordable Sequence-aware COntention Modeling in Crossbar-based MPSoCs. In 38th ACM/SIGAPP Symposium On Applied Computing (SAC 2023). Tallinn (Estonia), March 2023
ACM SAC			Roger Pujol, Mohamed Hassan, Hamid Tabani, Jaume Abella, Francisco J. Cazorla. Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems In 38th ACM/SIGAPP Symposium On Applied Computing (SAC 2023). Tallinn (Estonia), March 2023
ACM SAC			Roger Pujol, Mohamed Hassan, Hamid Tabani, Jaume Abella, Francisco J. Cazorla. Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems In 38th ACM/SIGAPP Symposium On Applied Computing (SAC 2023). Tallinn (Estonia), March 2023
AAAI			Axel Brando, Isabel Serra, Enrico Mezzetti, Francisco J. Cazorla, Jaume Abella. Standardizing the Probabilistic Sources of Uncertainty for the sake of Safety Deep Learning In SafeAI 2023 The AAAI's Workshop on Artificial Intelligence Safety. Washington, D.C., February 2023

Journals

Springer RTS			Miguel Alcon, Axel Brando, Enrico Mezzetti, Jaume Abella and Francisco J. Cazorla Main sources of variability and non-determinism in AD software: taxonomy and prospects to handle them. In Springer Springer Real-Time Systems Journal. August 2023
ELSEVIER JSA			Martí Caro, Hamid Tabani, Jaume Abella, Francesc Moll, Enric Morancho, Ramon Canal, Josep Alte, Antonio Calomarde, Francisco J. Cazorla, Antonio Rubio, Pau Fontova, Jordi Fornt An automotive case study on the limits of approximation for object detection. In ELSEVIER Journal of Systems Architecture. May 2023
IEEE Computer			Axel Brando, Isabel Serra, Enrico Mezzetti, Francisco J. Cazorla, Jon Perez-Cerrolaza, Jaume Abella On Neural Networks Redundancy and Diversity for Their Use in Safety-Critical Systems. In IEEE Computer. vol. 56. May 2023
ACM TODAES			Jordi Cardona, Carles Hernández, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla . Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems. In ACM Transactions on Design Automation of Electronic Systems. Volume 28, Issue 3. April 2023
IEEE Computer			Jon Perez-Cerrolaza, Francisco J. Cazorla, Jaume Abella. Uncertainty Management in Dependable and Intelligent Embedded Software. In Computer. vol. 56. March 2023.
Springer SQJ			Miguel Alcon, Hamid Tabani, Jaume Abella and Francisco J. Cazorla Dynamic and execution views to improve validation, testing, and optimization of autonomous driving. In Springer Software Quality Journal. February 2023
ACM TECS			Roger Pujol, Josep Jorba, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco Cazorla. Vector Extensions in COTS Processors to Increase Guaranteed Performance in Real-Time Systems. In ACM Transactions on Embedded Computing Systems. Volume 22, Issue 2. January 2023

2022

Conferences

ICSRS			Javier Fernández, Irune Agirre, Jon Perez-Cerrolaza, Francisco J. Cazorla and Jaume Abella. A Methodology for Selective Protection of Matrix Multiplications: a Diagnostic Coverage and Performance Trade-off for CNNs Executed on GPUs. In Proceedings of the 6th International Conference on System Reliability and Safety. Venice, Italy. November 2022.
ICCD			Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Jaume Abella, Francisco J. Cazorla. Contention Tracking in GPU Last-Level Cache. In Proceedings of the 40th International Conference On Computer Design (ICCD 2021). Lake Tahoe, California, USA. October 2022
ECRTS			Sergi Vilardell, Isabel Serra, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla, Joan del Castillo. Using Markov’s Inequality with Power-of-k Function for Probabilistic WCET Estimation. In Proceedings of the 34th Euromicro Conference on Real-Time Systems (ECRTS 2022). Modena, Italy. July 2022. Best Paper Award.
ECRTS			Axel Brando, Isabel Serra, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla. Using Quantile Regression in Neural Networks for Contention Prediction in Multicore Processors. In Proceedings of the 34th Euromicro Conference on Real-Time Systems (ECRTS 2022). Modena, Italy. July 2022.
ERTS			Raul de la Cruz, Phil Harris, Sam Thompson, Christos Evripidou, Tim Loveless, Juan M. Reina, Mikel Fernandez, Enrico Mezzetti, Francisco J. Cazorla. MASTECS Multicore Timing Analysis on an Avionics Vehicle Management Computer. In Proceedings of the 11th Embedded Real Times (ERTS 2022). Toulouse, France. June 2022. Best Paper Award.
ERTS			Sergi Alcaide, Guillem Cabo, Francisco Bas, Pedro Benedicte, Fabio Mazzocchetti, Francisco J. Cazorla, Jaume Abella. Unboxing the Sand: on Deploying Safety Measures in the Programmable Logic of COTS MPSoCs. In Proceedings of the 11th Embedded Real Times (ERTS 2022). Toulouse, France. June 2022

Journals

ACM CSUR			Jon Perez-Cerrolaza, Jaume Abella, Leonidas Kosmidis, Alejandro J. Calderon, Francisco Cazorla, Jose Luis Flores. GPU Devices for Safety-Critical Systems: A Survey. In ACM Computing Surveys (CSUR). Vol 55, No 7
MDPI			Javier Fernández,Jon Perez-Cerrolaza,Irune Agirre, Alejandro J. Calderon,Jaume Abella and Francisco J. Cazorla. On the Safe Deployment of Matrix Multiplication in Massively Parallel Safety-Related Systems. In MDPI Applied Scences. Apr 2022

2021

Conferences

ICCAD			Kazi Asifuzzaman, Mohamed Abuelala, Mohamed Hassan, Francisco J Cazorla. Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems. In Proceedings of the 40th International Conference On Computer Aided Design (ICCAD 2021). Virtual Event. November 2021
ICCD			Jeremy J. Giesen, Enrico Mezzetti, Jaume Abella Ferrer and Francisco J. Cazorla. PRL: Standardizing Performance Monitoring Library for High-Integrity Real-Time Systems. In Proceedings of the 39th International Conference On Computer Design (ICCD 2021). Virtual Conference. October 2021
DSD			Miguel Alcon, Hamid Tabani, Jaume Abella, Francisco J. Cazorla. Enabling Unit Testing of Already-Integrated AI-based Software Systems: The Case of Apollo for Autonomous Driving. In Proceedings of the Euromicro DSD (Digital System Design)/SEAA (Software Engineering and Advanced Applications) conference. Virtual Conference. August 2021
ECRTS			Alejandro Serrano-Cases, Juan M. Reina, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla. Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC In Proceedings of the 33rd Euromicro Conference on Real-Time Systems (ECRTS 2021). Virtual Event. July 2021
ACM SAC			Sergi Vilardell, Isabel Serra, Hamid Tabani, Jaume Abella, Joan del Castillo, Francisco J. Cazorla. MUCH: Exploiting Pairwise Hardware Event Monitor Correlations for Improved Timing Analysis of Complex MPSoCs In The 36th ACM/SIGAPP Symposium On Applied Computing (SAC)Virtual Event. March 2021
DATE			Roger Pujol, Hamid Tabani, Jaume Abella, Mohamed Hassan, and Francisco J. Cazorla Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP’s T2080 Cache Coherence. In the Design, Automation and Test in Europe Conference (DATE 2021). Grenoble (France), March 2021 .

Journals

SAE			Francisco J. Cazorla, Jaume Abella, Enrico Mezzetti. Dissecting Robust Resource Partitioning, Robust Time Partitioning, and Robust Partitioning in CAST-32A. Nov 2021 In SAE Automotive Technical Papers. Nov 2021
ELSEVIER JSA			Javier Fernandez, Jon Pérez, Irune Agirre, Imanol Allende, Jaume Abella, Francisco J. Cazorla Towards functional safety compliance of matrix-matrix multiplication for machine learning-based autonomous systems. In ELSEVIER Journal of Systems Architecture. 2021
Springer Computing			Hamid Tabani, Roger Pujol, Miguel Alcon, Joan Moya, Jaume Abella, Francisco J. Cazorla. ADBench: Benchmarking Autonomous Driving Systems In Springer Computing Journal. 2021
SAE			Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla. On the Definition of Resource Sharing Levels to Understand and Control the Impact of Contention in Multicore Processors In SAE Automotive Technical Papers. Jun 2021
IEEE TETC			Gabriel Fernandez, Jaume Abella, Guillem Bernat, Francisco J Cazorla. Surrogate Applications for Early Design Stage Multicore Contention Modeling. In IEEE Transactions on Emerging Topics in Computing. Vol 9, No 1. Jan-March 2021
ELSEVIER JPDC			Hamid Tabani, Fabio Mazzocchetti, Pedro Benedictea, JaumeAbella, Francisco J.Cazorla. Performance Analysis and Optimization Opportunities for NVIDIA Automotive GPUs In ELSEVIER Journal of Parallel and Distributed Computing. Vol 152. Jan 2021

2020

Conferences

IEEE TCAD ESWEEK (EMSOFT)			Sergi Vilardell, Isabel Serra, Roberto Santalla, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol XX, No YY. Sept 2020
DSD			Irune Agirre, Peio Onaindia, Tomaso Poggi, Irune Yarza, Francisco J. Cazorla, Leonidas Kosmidis, Kim Gruttner, Mohammed Abuteir, Jan Loewe, Juan Maria Orbegozo and Stefania Botta UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems. In Proceedings of the 31st Euromicro DSD (Digital System Design)/SEAA (Software Engineering and Advanced Applications) conference. Portorož, Slovenia. August 2020
DATE			Ivan Rodriguez, Leonidas Kosmidis, Olivier Notebaert, Francisco J. Cazorla, David Steenari An On-board Algorithm Implementation on an Embedded GPU: A Space Case. In the Design, Automation and Test in Europe Conference (DATE 2020). Grenoble (France), April - June 2020 .
ECRTS			Xavier Palomo, Mikel Fernández, Sylvain Girbal, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla, Laurent Rioux. Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study In Proceedings of the 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020) Modena, Italy. July 2020
ISORC			Hamid Tabani, Roger Pujol, Jaume Abella, Francisco J. Cazorla. A Cross-Layer Review of Deep Learning Frameworks to Ease Their Optimization and Reuse IEEE International Symposium On Real-Time Computing (ISORC) Nashville, TN, USA. May, 2020.
RTAS			Jeremy Giesen, Pedro Benedicte, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla. Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP) In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) Sydney, Australia. April 2020
RTAS			Miguel Alcon, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla. Timing of Autonomous Driving Software: Problem Analysis and Prospects for Future Solutions In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) Sydney, Australia. April 2020
ACM SAC			Sergi Vilardell, Isabel Serra, Hamid Tabani, Jaume Abella, Joan del Castillo, Francisco J. Cazorla. CleanET: enabling timing validation for complex automotive systems In The 35th ACM/SIGAPP Symposium On Applied Computing (SAC)Brno, Czech Republic. April 2020
ACM SAC			Hamid Tabani, Matteo Fusi, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla. IntPred: flexible, fast, and accurate object detection for autonomous driving systems In The 35th ACM/SIGAPP Symposium On Applied Computing (SAC)Brno, Czech Republic. April 2020
ACM SAC			Javier Barrera, Leonidas Kosmidis, Hamid Tabani, Enrico Mezzetti, Jaume Abella, Mikel Fernández, Guillem Bernat, Francisco J. Cazorla. On the reliability of hardware event monitors in MPSoCs for critical domains In The 35th ACM/SIGAPP Symposium On Applied Computing (SAC)Brno, Czech Republic. April 2020
ACM SAC			Miguel Alcon, Hamid Tabani, Jaume Abella, Leonidas Kosmidis, Francisco J. Cazorla. En-Route: on enabling resource usage testing for autonomous driving frameworks In The 35th ACM/SIGAPP Symposium On Applied Computing (SAC)Brno, Czech Republic. April 2020

Journals

ACM CSUR			Jon Perez, Roman Obermaisser, Jaume Abella, Francisco J. Cazorla, Kim Gruttner, Irune Agirre, Hamidreza Ahmadian, Imanol Allende. Multi-Core Devices for Safety-Critical Systems: A Survey. In ACM Computing Surveys (CSUR). Vol 53, No 4
ACM TECS			Alejandro Josué Calderón, Leonidas Kosmidis, Carlos Fernando Nicolás, Francisco J. Cazorla, Peio Onaindia. GMAI: Understanding and Exploiting the Internals of GPU Resource Allocation in Critical Systems. In ACM Transactions on Embedded Computing Systems,Volume XX Issue YY. May 2020.
Embedded.com			Francisco J. Cazorla, Enrico Mezzetti, Ian Broster, Juan Valverde, Stefania Botta, Jaume Abella, Christos Evripidou, Javier Mora de Sambricio. Ensuring software timing behavior in critical multicore-based embedded systems. In Embedded.com. Technical Article.July 2020.

2019

Conferences

ICCAD			Alejandro J. Calderon, Leonidas Kosmidis, Carlos F. Nicolas, Francisco J. Cazorla, Peio Onaindia Understanding and Exploiting the Internals of GPU Resource Allocation for Critical Systems. In Proceedings of the 38th International Conference On Computer Aided Design (ICCAD 2019) Westminster (CO), USA. November 2019
DSD			David Trilla, Carles Hernandez, Jaume Abella and Francisco J. Cazorla Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation. In Proceedings of the 31st Euromicro DSD (Digital System Design)/SEAA (Software Engineering and Advanced Applications) conference. Kallithea, Greece. August 2019
DSD			David Trilla, Carles Hernandez, Jaume Abella and Francisco J. Cazorla An Approach for Detecting Power Peaks during Testing and Breaking Systematic Pathological Behavior. In Proceedings of the 31st Euromicro DSD (Digital System Design)/SEAA (Software Engineering and Advanced Applications) conference. Kallithea, Greece. August 2019
WCET Workshop			Jeremy Giesen, Enrico Mezzetti, Enrique Fernandez, Jaume Abella and Francisco J Cazorla. ePAPI: Performance Application Programming Interface for Embedded Platforms In WCET Analysis Workshop (WCET). Stuttgart, Germany. July 2019
ECRTS			Roger Pujol, Hamid Tabani, Leonidas Kosmidis, Enrico Mezzetti, Jaume Abella, Francisco J. Cazorla Generating and Exploiting Deep Learning Variants to Increase Utilization of the Heterogeneous Resources in the NVIDIA Xavier. In Proceedings of the 31st Euromicro Conference on Real-Time Systems (ECRTS 2019) Stuttgart, Germany. July 2019
DAC			Hamid Tabani, Leonidas Kosmidis, Jaume Abella, Guillem Bernat, Francisco J. Cazorla Assessing the Adherence of Industrial Autonomous Driving Software to ISO-26262 Guidelines for Software. In Proceedings of the 56th Design Automation Conference (DAC) Las Vegas (NV), USA. June 2019
RTAS			Xavier Palomo, Enrico Mezzetti, Jaume Abella, Reinder J. Bril, Francisco J. Cazorla Accurate ILP-based contention modeling on statically scheduled multicore systems. In Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) Montreal, Canada. April 2019
DATE			Pedro Benedicte, Carles Hernandez, Jaume Abella, Francisco J. Cazorla LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache. In Proceedings of the Design Automation and Test in Europe) (DATE 2019) Florence, Italy, March 2019
DATE			Jordi Cardona, Carles Hernandez, Jaume Abella, Francisco J. Cazorla Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement. In Proceedings of the Design Automation and Test in Europe) (DATE 2019) Florence, Italy, March 2019
DATE			Enrico Mezzetti, Luca Barbina, Jaume Abella, Stefania Botta and Francisco J. Cazorla AURIX TC277 Multicore Contention Model Integration for Automotive Applications. In Proceedings of the Design Automation and Test in Europe) (DATE 2019) Florence, Italy, March 2019
DATE			Mikel Fernandez, Gabriel Fernandez, Jaume Abella, Francisco J. Cazorla Multicore Early Design Stage Guaranteed Performance Assessment for the Space Domain. In Proceedings of the Design Automation and Test in Europe) (DATE 2019) Florence, Italy, March 2019
ASP-DAC			Pedro Benedicte, Jaume Abella, Enrico Mezzetti, Carles Hernandez, Francisco J. Cazorla Towards Limiting the Impact of Timing Anomalies in Complex Real-Time Processors. In 24th Asia and South Pacific Design Automation Conference (ASP-DAC). Tokyo, Japan. January 21-24, 2019

Journals

IEEE SC			David Trilla, Carles Hernandez, Jaume Abella, Francisco J. Cazorla. Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices. In IEEE Transactions on Sustainable Computing. Volume - Issue -, 2019.
IEEE D&T			David Trilla, Carles Hernandez, Jaume Abella, Francisco J. Cazorla Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors In IEEE Design & Test. Vol XX, No XX
ACM CSUR			Francisco J. Cazorla, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernandez, Jaume Abella, Tullio Vardanega Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey In ACM Computing Surveys (CSUR). Vol 52, No 1
IEEE ToC			Suzana Milutinovic, Jaume Abella, Enrico Mezzetti and Francisco J. Cazorla Increasing the Reliability of Software Timing Analysis for Cache-Based Processors In IEEE Transactions on Computers. Vol xx, No yy

2018

Conferences

RTSS			Jordi Cardona, Carles Hernandez, Enrico Mezzetti, Jaume Abella and Francisco J. Cazorla. NoCo: ILP-based Worst-Case Contention Estimation for Mesh Real-Time Manycores. In 39th IEEE Real-Time Systems Symposium (RTSS). Dec 2018, Nashville (Tennesse), USA.
ICCAD			Leonidas Kosmidis, Cristian Maxim, Victor Jegu, Francis Vatrinet, Francisco J. Cazorla. Industrial Experiences with Resource Management Under Software Randomization in ARINC653 Avionics Environments. In International Conference On Computer Aided Design (ICCAD). Nov 5-8 2018, San Diego (California), USA.
ECRTS			Pedro Benedicte, Carles Hernandez, Jaume Abella and Francisco J. Cazorla. HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET. In 30th Euromicro Conference on Real-Time Systems (ECRTS). Jul 2018, Barcelona, Spain.
DAC			Suzana Milutinovic, Jaume Abella, Enrico Mezzetti and Francisco J. Cazorla. Measurement-Based Cache Representativeness on Multipath Programs. In Proceedings of the 55th Annual Design Automation Conference (DAC). Jun 2018, San Francisco, USA.
DAC			Enrique Díaz, Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla. Modelling Multicore Contention on the AURIX(TM) TC27x. In Proceedings of the 55th Annual Design Automation Conference (DAC). Jun 2018, San Francisco, USA.
DAC			David Trilla, Carles Hernandez, Jaume Abella and Francisco J. Cazorla. Cache Side-Channel Attacks and Time-Predictability in High-Performance Critical Real-Time Systems. In Proceedings of the 55th Annual Design Automation Conference (DAC). Jun 2018, San Francisco, USA. Best Paper Award Nominee.
DATE			Pedro Benedicte, Carles Hernández, Jaume Abella, Francisco J. Cazorla Design and integration of hierarchical-placement multi-level caches for real-time systems. In Proceedings of the Design Automation and Test in Europe) (DATE 2018) Dresden, Germany, March 2018
ERTS2			Gabriel Fernandez, Francisco J. Cazorla, Jaume Abella. Consumer Electronics Processors for Critical Real-Time Systems: a (Failed) Practical Experience. In 9th European Congress on Embedded Real Time Software and Systems (ERTS 2018). Jan 2018, Toulouse, France.

Journals

IEEE Micro			Sergi Alcaide, Leonidas Kosmidis, Hamid Tabani, Carles Hernandez, Jaume Abella, Francisco J. Cazorla. Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain. In IEEE Micro. Micro special issue on Hardware Acceleration. Vol 38, No 6. Nov/Dec 2018.
IEEE TCAD ESWEEK (CODES+ISSS)			Jordi Cardona, Carles Hernandez, Jaume Abella, and Francisco J. Cazorla. EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol XX, No YY. Oct 2018
IEEE ToR			Irune Agirre, Francisco J. Cazorla, Jaume Abella, Carles Hernandez, Enrico Mezzetti, Mikel Azkarate-askatsua, Tullio Vardanega Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262 In IEEE Transactions on Reliability. Vol XX, No YY, May 2018.
IEEE Design & Test			Francisco J. Cazorla, Jaume Abella, Enrico Mezzetti, Carles Hernandez, Tullio Vardanega, Guillem Bernat Reconciling Time Predictability and Performance in Future Computing Systems In IEEE Design and Test (Special Issue on Time-Critical Systems Design). Vol 35, No 2, April 2018.
IEEE Micro			Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V & V In IEEE Micro (Special Issue on Automotive Computing). Vol 38, No 1, Jan 2018.

2017

Conferences

ECRTS			Carles Hernández, Jaume Abella, Francisco J. Cazorla, Alen Bardizbanyan, Jan Andersson, Fabrice Cros, Franck Wartel. Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study. In 29th Euromicro Conference on Real-Time Systems, (ECRTS). Dubrovnik, Croatia. June 27-30, 2017
Ada-Europe			Suzana Milutinovic, Jaume Abella, Irune Agirre, Mikel Azkarate-Askasua, Enrico Mezzetti, Tullio Vardanega, Francisco J. Cazorla. Software Time Reliability in the Presence of Cache Memories. In 22nd International Conference on Reliable Software Technologies (Ada-Europe). Vienna, Austria, 12-16 June 2017
Ada-Europe			Enrique Díaz, Mikel Fernández, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernández, Jaume Abella, Francisco J. Cazorla. MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding. In 22nd International Conference on Reliable Software Technologies (Ada-Europe). Vienna, Austria, 12-16 June 2017
RTAS			Enrico Mezzetti, Mikel Fernandez, Alen Bardizbanyan, Irune Agirre, Jaume Abella, Tullio Vardanega and Francisco J Cazorla. EPC Enacted: Integration in an Industrial Toolbox and Use Against a Railway Applicatione In 2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). Pittsburgh, PA, USA. April 2017
DATE			Fabrice Cros, Leonidas Kosmidis, Franck Wartel, David Morales, Jaume Abella, Ian Broster, Francisco J. Cazorla Dynamic Software Randomisation: Lessons Learned From an Aerospace Case Study In Proceedings of the Design Automation and Test in Europe) (DATE 2017) Lausanne, Switzerland, March 2017
DATE			Mikel Fernandez, David Morales, Leonidas Kosmidis, Alen Bardizbanyan, Ian Broster, Carles Hernandez, Eduardo Quiñones, Jaume Abella, Francisco Cazorla, Paulo Machado, Luca Fossati Probabilistic Timing Analysis on Time-Randomized Platforms for the Space Domain In Proceedings of the Design Automation and Test in Europe) (DATE 2017) Lausanne, Switzerland, March 2017
DATE			Mladen Slijepcevic, Carles Hernandez, Jaume Abella, Francisco J. Cazorla Design and Implementation of a Fair Credit-Based Bandwidth Sharing Scheme for Buses In Proceedings of the Design Automation and Test in Europe) (DATE 2017) Lausanne, Switzerland, March 2017

Journals

IJDATS			Joan del Castillo, Maria Padilla, Jaume Abella, Francisco J. Cazorla Execution time distributions in embedded safety-critical systems using extreme value theory In International Journal of Data Analysis Techniques and Strategies. Vol 9, No 4, 2017.
IEEE TDMR			David Trilla, Carles Hernandez, Jaume Abella, Francisco Cazorla Aging Assessment and Design Enhancement of Randomized Cache Memories In IEEE Transactions on Device and Materials Reliability. Vol 17, No 1, January 2017.
EURASIP JES			Suzana Milutinovic, Jaume Abella and Francisco J. Cazorla. On the assessment of probabilistic WCET estimates reliability for arbitrary programs In EURASIP Journal on Embedded Systems.
IEEE ToC			Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla. Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration. In IEEE Transactions on Computers. Volume 6 Issue 4, 2017.
ACM TODAES			Jaume Abella, Maria Padilla, Joan Del Castillo, Francisco J. Cazorla Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation In ACM Transactions on Design Automation of Electronic Systems (TODAES): Volume 22 Issue 4, June 2017.
ELSEVIER MandM			Milos Panic, Jaume Abella, Eduardo Quiñones, Carles Hernandez, Theo Ungerer, Francisco J. Cazorla Adapting TDMA Arbitration for Measurement-Based Probabilistic Timing Analysis In ELSEVIER Microprocessors and Microsystems: Volume XX, Issue YY, June 2017.

2016

Conferences

ICCAD			TASA: toolchain-agnostic static software randomisation for critical real-time systems Leonidas Kosmidis, Roberto Vargas, David Morales, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla
SASSUR			Irune Agirre, Mikel Azkarate-Askasua, Asier Larrucea Ortube, Jon Perez, Tullio Vardanega and Francisco J Cazorla. Automotive Safety Concept Definition for Mixed -Criticality Integration on a COTS Multicore In 5th International Workshop on Next Generation of System Assurance Approaches for Safety-Critical Systems (SASSUR). Trondheim, Norway. September 2016
DSD/SEAA			Mladen Slijepcevic, Mikel Fernandez, Carles Hernandez, Jaume Abella, Eduardo Quiñones and Francisco J Cazorla pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed- Analysis In 19th Euromicro Conference on Digital Systems Design (DSD/SEAA). Limassol, Cyprus. August 2016.
DSD/SEAA			Francisco J Cazorla, Jaume Abella, Jan Anderson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-Askasua, Franck Wartel, Liliana Cucu, Fabrice Cross, Glenn Farrall, Adriana Gogonel, Andrea Gianarro, Benoît Triquet, Carles Hernandez, Code Lo, Cristian Maxim, David Morales, Eduardo Quiñones, Enrico Mezzetti, Leonidas Kosmidis, Irune Agirre, Mikel Fernandez, Mladen Slijepcevic, Philippa Conmy and Walid Talaboulma PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis (Invited Paper) In 42nd Euromicro conference on Software Engineering and Advanced Applications (SEAA) (DSD/SEAA). Limassol, Cyprus. August 2016.
INDIN			Pedro Benedicte, Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla A Confidence Assessment of WCET Estimates for Software Time Randomized Caches In 2016 IEEE International Conference on Industrial Informatics (INDIN). Futuroscope-Poitiers, France. July 2016
WCET Workshop			Enrique Diaz, Jaume Abella, Enrico Mezzetti, Irune Agirre, Mikel Azkarate-Askasua, Tullio Vardanega and Francisco J Cazorla. Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis In WCET Analysis Workshop (WCET). Toulouse, France. July 2016
WCET Workshop			Leonidas Kosmidis, Davide Compagnin, David Morales, Enrico Mezzetti, Eduardo Quiñones, Jaume Abella, Tullio Vardanega and Francisco J Cazorla Measurement-Based Timing Analysis of the AURIX Caches In WCET Analysis Workshop (WCET). Toulouse, France. July 2016
IOLTS			David Trilla, Carles Hernandez, Jaume Abella, Francisco J. Cazorla Resilient Random Modulo Cache Memories for Probabilistically-Analyzable Real-Time Systems In 22nd IEEE International On-Line Testing Symposium (IOLTS). Sant Feliu de Guixols (Spain). July 2016
DAC			Random modulo: a new processor cache design for real-time critical systems Carles Hernandez, Jaume Abella, Andrea Gianarro, Jan Andersson, Francisco J. Cazorla Proceedings of the 53rd Annual Design Automation Conference, 2016
ISORC			Suzana Milutinovic, Jaume Abella and Francisco J Cazorla Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns In IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC). York, United Kingdom. MAY, 2016 Best Paper Award Nominee.
SIES			Javier Jalle, Eduardo Quiñones, Jaume Abella, Luca Fossati, Marco Zulianello and Francisco J Cazorla Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems In 11th IEEE International Symposium on Industrial Embedded Systems (SIES). Krakow, Poland. May 2016
SIES			Javier Jalle, Mikel Fernandez, Jaume Abella, Jan Andersson, Matthieu Patte, Luca Fossati, Marco Zulianello and Francisco J Cazorla Contention-Aware Performance Monitoring Counter Support for Real-Time MPSoCs In 11th IEEE International Symposium on Industrial Embedded Systems (SIES). Krakow, Poland. May 2016
SIES			Pedro Benedicte, Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella and Francisco J. Cazorla Modeling the Confidence of Timing Analysis for Time Randomised Caches In 11th IEEE International Symposium on Industrial Embedded Systems (SIES). Krakow, Poland. May 2016
RTAS			David Trilla, Javier Jalle, Mikel Fernandez, Jaume Abella and Francisco J. Cazorla Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems In 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). Vienna, Austria. April 2016
RTAS			Milos Panic, Carles Hernandez, Eduardo Quiñones, Jaume Abella and Francisco J. Cazorla Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems In 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). Vienna, Austria. April 2016
DATE			Milos Panic, Carles Hernandez, Jaume Abella, Antoni Roca Perez, Eduardo Quiñones, Francisco J. Cazorla Improving Performance Guarantees in Wormhole Mesh NoC Designs In Proceedings of the Design Automation and Test in Europe) (DATE 2016)Dresden, Germany, March 2016
DATE			Sebastian Kehr, Milos Panic, Eduardo Quiñones, Bert Boeddeker, Jorge Becerril Sandoval, Jaume Abella, Francisco J. Cazorla, Gunter Schafer Maximizing Runnable-level Parallelism in AUTOSAR Applications In Proceedings of the Design Automation and Test in Europe) (DATE 2016) Dresden, Germany, March 2016

Journals

ACM TODAES			DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems Qixiao Liu, Miquel Moreto, Jaume Abella, Francisco J. Cazorla, Mateo Valero ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016
IEEE ToC			Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones Tullio Vardanega, Francisco Cazorla Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration In IEEE Transaction on Computers. Vol PP, No 99
ELSEVIER MandM			Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Carles Hernandez, Andrea Gianarro, Ian Broster, Francisco J. Cazorla Fitting Processor Architectures for Measurement-Based Probabilistic Timing Analysis In ELSEVIER Microprocessors and Microsystems. Vol 47, Part B.
ACM TECS			Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore Theo Ungerer, Christian Bradatsch, Martin Frieb, Florian Kluge, Jörg Mische, Alexander Stegmeier, Ralf Jahr, Mike Gerdes, Pavel Zaykov, Lucie Matusova, Zai Jian Jia Li, Zlatko Petrov, Bert Böddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cassé, Armelle Bonenfant, Pascal Sainrat, Nick Lay, David George, Ian Broster, Eduardo Quiñones, Milos Panic, Jaume Abella, Carles Hernandez, Francisco Cazorla, Sascha Uhrig, Mathias Rohde, Arthur Pyka ACM Transactions on Embedded Computing Systems (TECS), 2016
IEEE ToC			Petar Radojkovic, Paul M Carpenter, Miquel Moreto, Vladimir Cakarevic, Javier Verdu, Alex Pajuelo, Francisco J Cazorla, Mario Nemirovsky, Mateo Valero Thread assignment in multicore/multithreaded processors: A statistical approach In IEEE Transactions on Computers. Vol 65, No 1

2015

Conferences

RTSS			Marco Ziccardi, Enrico Mezzetti, Tullio Vardanega, Jaume Abella, Francisco J. Cazorla EPC: Extended Path Coverage for Measurement-based Probabilistic Timing Analysis In IEEE Real-Time Systems Symposium (RTSS) San Antonio (Texas), December 2015
DASC			Irune Agirre, Mikel Azkarate-askasua, Asier Larrucea, Jon Perez, Tullio Vardanega, Francisco J. Cazorla A safety concept for a railway mixed-criticality embedded system based on multicore partitioning In 13th IEEE Int. Conference on Dependable, Autonomic and Secure Computing (DASC-2015) Liverpool, UK. October 2015
DSD			Irune Agirre, Mikel Azkarate-Askasua, Jon Perez, Carles Hernandez, Jaume Abella, Tullio Vardanega, Francisco J. Cazorla IEC-61508 SIL 3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis In 18th Euromicro Conference on Digital System Design (special session on Mixed Criticality System Design, Implementation and Analysis) (DSD) Madeira, Portugal. August 2015
DSD			Milos Panic, Jaume Abella, Carles Hernandez, Eduardo Quiñones, Theo Ungerer, Francisco J. Cazorla Enabling TDMA Arbitration in the Context of MBPTA In 18th Euromicro Conference on Digital System Design (special session on Mixed Criticality System Design, Implementation and Analysis) (DSD) Madeira, Portugal. August 2015
DSD			Milos Panic, Eduardo Quiñones, Carles Hernandez, Jaume Abella, Francisco J. Cazorla CAP: Communication-aware Allocation Algorithm for Real-Time Parallel Applications on Many-cores In 18th Euromicro Conference on Digital System Design (special session on Mixed Criticality System Design, Implementation and Analysis) (DSD) Madeira, Portugal. August 2015
SIES			Jaume Abella, Carles Hernandez, Eduardo Quiñones, Francisco J. Cazorla, Philippa Ryan Conmy, Mikel Azkarate-askasua, Jon Perez, Enrico Mezzetti, Tullio Vardanega WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness In 10th IEEE International Symposium on Industrial Embedded Systems (SIES) Siegen, Germany. June 2015
DAC			Increasing confidence on measurement-based contention bounds for real-time round-robin buses Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla DAC '15 Proceedings of the 52nd Annual Design Automation Conference, 2015
DAC			Resource usage templates and signatures for COTS multicore processors Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla DAC '15 Proceedings of the 52nd Annual Design Automation Conference, 2015
DAC			PACO: fast average-performance estimation for time-randomized caches Suzana Milutinovic, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla Proceedings of the 52nd Annual Design Automation Conference, 2015
ICRA			Jaume Abella, Joan del Castillo, Francisco J. Cazorla, Maria Padilla Extreme value theory in computer sciences: The case of embedded safety-critical systems In 6th International Conference on Risk Analysis (ICRA) Barcelona, Spain. May 2015
ISORC			Gabriel Fernandez, Jaume Abella, Eduardo Qui~nones, Luca Fossati, Marco Zulianello, Tullio Vardanega, Francisco J. Cazorla Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors In IEEE International Symposium On Real-Time Computing (ISORC) Auckland, New Zealand. April, 2015.
SAC			Introduction to partial time composability for COTS multicores Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Luca Fossati, Marco Zulianello, Francisco J. Cazorla Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015
DATE			Franck Wartel, Leonidas Kosmidis, Adriana Gogonel, Andrea Baldovin, Zoe Stephenson, Benoit Triquet, Eduardo Quiñones, Code Lo, Enrico Mezzetti, Ian Broster, Jaume Abella, Liliana Cucu-Grosjean, Tullio Vardanega, Francisco Cazorla Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms. In 18th Design, Automation and Test in Europe Conference (DATE). Grenoble (France), March 9-13 2015 .
ARCS			Suzana Milutinovic, Jaume Abella, Damien Hardy, Eduardo Quiñones, Isabelle Puaut, Francisco J. Cazorla Speeding up Static Probabilistic Timing Analysis. In 28th GI/ITG International Conference on Architecture of Computing Systems (ARCS). Porto (Portugal), March 24-27 2015.
HPCA			Victor Jimenez, Alper Buyuktosunoglu, Pradip Bose, Franck O’Connell, Francisco J. Cazorla, Mateo Valero Increasing Multicore System Efficiency through Intelligent Bandwidth Shifting. In International Symposium on High- Performance Computer Architecture (HPCA). San Francisco Bay Area, California, USA. February 7-11, 2015,

Journals

LITES			Enrico Mezzetti, Marco Ziccardi, Tullio Vardanega, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems In Leibniz Transactions on Embedded Systems (LITES). Vol 2, No 1 (2015)
ACM TACO			Sensible Energy Accounting with Abstract Metering for Multicore Systems Qixiao Liu, Miquel Moreto, Jaume Abella, Francisco J. Cazorla, Daniel A. Jimenez, Mateo Valero ACM Transactions on Architecture and Code Optimization (TACO), 2015

2014

Conferences

RTSS			Javier Jalle, Eduardo Quiñones, Jaume Abella, Luca Fossati, Marco Zulianello and Francisco J. Cazorla A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation for a Space Case Study. In IEEE Real-Time Systems Symposium (RTSS). Roma, Italy. December, 2014.
EMSOFT			Parallel many-core avionics systems MiloÅ¡ Panić, Eduardo Quiñones, Pavel G. Zaykov, Carles Hernandez, Jaume Abella, Francisco J. Cazorla EMSOFT '14 Proceedings of the 14th International Conference on Embedded Software, 2014
CODES+ISSS			RunPar: an allocation algorithm for automotive applications exploiting runnable parallelism in multicores MiloÅ¡ Panić, Sebastian Kehr, Eduardo Quiñones, Bert Boddecker, Jaume Abella, Francisco J. Cazorla CODES '14 Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
EUROPAR			Qixiao Liu, Miquel Moreto, Jaume Abella, Francisco J. Cazorla and Mateo Valero DReAM: Per-Task DRAM Energy Metering in Multicore Systems. In 20th International EUROPAR Conference. European Conference on Parallel and Distributed Computing (EUROPAR). Porto, Portugal. August, 2014.
DSD			Leonidas Kosmidis , Eduardo Quiñones, Jaume Abella, Tullio Vardanega, Ian Broster, Francisco J. Cazorla Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture. In Euromicro Euromicro Conference on Digital System Design (DSD) Verona, Italy. August, 2014.
ECRTS			Jaume Abella, Damien Hardy, Isabelle Puaut, Eduardo Quiñones, Francisco J. Cazorla On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques. In Euromicro Conference on Real-Time Systems (ECRTS) Madrid, Spain. July, 2014.
ECRTS			Leonidas Kosmidis, Jaume Abella, Franck Wartel, Eduardo Quiñones, Antoine Collin, Francisco J. Cazorla PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis. In Euromicro Conference on Real-Time Systems (ECRTS) Madrid, Spain. July, 2014.
ECRTS			Jaume Abella, Eduardo Quiñones, Franck Wartel, Tullio Vardanega, Francisco J. Cazorla Heart of Gold: Making the Improbable Happen to Extend Coverage in Probabilistic Timing Analysis. In Euromicro Conference on Real-Time Systems (ECRTS) Madrid, Spain. July, 2014.
WCET Workshop			Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Christine Rochange, Tullio Vardanega and Francisco J. Cazorla. Contention in multicore hardware shared resources: Understanding of the state of the art. In 14th International Workshop on Worst-Case Execution Time Analysis. Madrid, Spain. July, 2014.
DAC			Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems Mladen Slijepcevic, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla DAC '14 Proceedings of the 51st Annual Design Automation Conference, 2014
DAC			Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Glenn Farrall, Franck Wartel, Francisco J. Cazorla DAC '14 Proceedings of the 51st Annual Design Automation Conference, 2014 Best Paper Award.
RTAS			Javier Jalle, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello and Francisco J. Cazorla AHRB: A High-Performance Time-Composable AMBA AHB Bus In The 20th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2014). Berlin, Germany. April 2014.
DATE			Javier Jalle, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla Bus Designs for Time-Probabilistic Multicore Processors In The Design, Automation, and Test in Europe (DATE) conference. Dresden, Germany. March 2014.

Journals

IEEE CAL			Qixiao Liu, Victor Jimenez, Miquel Moreto, Jaume Abella, Francisco J. Cazorla and Mateo Valer Per-task Energy Accounting in Computing Systems. In IEEE Computer Architecture Letters (CAL).,Volume 13 Issue 2, July-Dec 2014.
IEEE Micro			Mladen Slijepcevic, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones and Francisco J. Cazorla. Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments. In IEEE Micro (Special Series on Harsh Chips) Volume X Issue Y, July 2014.
ACM TOPC			Adaptive Prefetching on POWER7: Improving Performance and Power Consumption Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Pradip Bose, Francis P. O’Connell, Bruce G. Mealey ACM Transactions on Parallel Computing - Inaugural Issue and Special Section on Top Papers from PACT-21, and Regular Papers, 2014
ACM TACO			Hardware support for accurate per-task energy metering in multicore systems Qixiao Liu, Miquel Moreto, Victor Jimenez, Jaume Abella, Francisco J. Cazorla, Mateo Valero ACM Transactions on Architecture and Code Optimization (TACO), 2013

2013

Conferences

RTSS			Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla. Multi-Level Unified Caches for Probabilistically Time Analysable Real-Time Systems. In IEEE Real-Time Systems Symposium (RTSS). Vancoubver, Canada. December
RTNS			Milos Panic, Jaume Abella, Eduardo Quiñones, German Rodriguez, Francisco J. Cazorla. On-Chip Ring Network Designs for Hard-Real Time Systems. In 21st International Conference on Real-Time Networks and Systems (RTNS). Sophia Antipolis, France. October 2013.
ECRTS			Mladen Slijepcevic, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla. DTM: Degraded Test Mode for Fault-Aware Probabilistic Timing Analysis. In 25th IEEE Euromicro Conference on Real-Time Systems. Paris, France. July
DSD			Theo Ungerer, Christian Bradatsces, Florian Kluge, Ralf Jahr, Jorg Mische, Joao Fernandes , Pavel Zaykov, Petrov Zlatko , Bert Boddeker, Sebastian Kehr, Hans Regler, Andreas Hugl, Christine Rochange, Haluk Ozaktas, Hugues Cases, Bonenfant Armelle , Pascal Sainrat, Nick Lay, Ian Broster, David George, Milos Panic, Eduard Quiñones, Francisco J. Cazorla, Jaume Abella, Sascha Uhrig, Mathias Rohde and Arthur Pyka. parMERASA - Multi-Core Execution of Parallelised Hard Real-Time Applications Supporting Analysability. In Euromicro Conference on Digital System Design. Santander, Spain. September
WCET Workshop			Francisco J Cazorla, Tullio Vardanega, Eduardo Quiñones and Jaume Abella. Upper-bounding Program Execution Time with Extreme Value Theory. In 13th International Workshop on Worst-Case Execution Time Analysis. Paris, France. July
WCET Workshop			Leonidas Kosmidis, Tullio Vardanega, Jaume Abella, Eduardo Quiñones and Francisco J Cazorla Measurement-Based Probabilistic Timing Analysis to Buffer Resources. In 13th International Workshop on Worst-Case Execution Time Analysis. Paris, France. July
SIES			Javier Jalle, Jaume Abella, Eduardo Quiñones, Luca Fossati, Marco Zulianello, Francisco J. Cazorla. Deconstructing Bus Access Control Policies for Real-Time Multicores. In 2013 8th IEEE International Symposium on Industrial Embedded Systems. Porto, Portugal. June 2013.
SIES			Franck Wartel, Leonidas Kosmidis, Code Lo, Benoit Triquet, Eduardo Quiñones, Jaume Abella, Adriana Gogonel, Andrea Baldovin, Enrico Mezzetti, Liliana Cucu, Tullio Vardanega, Francisco J. Cazorla . Measurement-Based Probabilistic Timing Analysis: Lessons from an Integrated-Modular Avionics Case Study. In 2013 8th IEEE International Symposium on Industrial Embedded Systems. Porto, Portugal. June 2013.
DAC			Sylvain Girbal, Miquel Moreto, Arnaud Grasset, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Sami Yehia On the convergence of high-performance and mission critical markets. In Design Automation Conference. Austin, Texas (USA). June
ISORC			Leonidas Kosmidis, Eduardo Qui�ones, Jaume Abella, Tullio Vardanega and Francisco Cazorla. Achieving Timing Composability with Measurement-Based Probabilistic Timing Analysis. In IEEE International Symposium on Object/component/service-oriented Real-time distributed computing. Paderborn, Germany. June 2013.
DATE			Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones and Francisco Cazorla. Cache Design for Probabilistic Real-Time Systems. In The Design, Automation, and Test in Europe (DATE) conference. Grenoble, France. March 2013.
DATE			Leonidas Kosmidis, Charlie Curtsinger, Eduardo Quiñones, Jaume Abella, Emery Berger and Francisco Cazorla. Probabilistic Timing Analysis on Conventional Cache Designs. In The Design, Automation, and Test in Europe (DATE) conference. Grenoble, France. March 2013.

Journals

IEEE TPDS			Petar Radojkovic, Vladimir Cakarevic, Javier Verdu, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors. In IEEE Transactions on Parallel and Distributed Systems (TPDS).,Volume 24 Issue 12, October 2013.
IEEE ToC			Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones and Francisco J. Cazorla. Efficient Cache Designs for Probabilistically Analysable Real-Time Systems. In IEEE Transactions on Computers (ToC).,Volume 63 Issue 12, 2013.
ACM TECS			Marco Paolieri, Eduardo Quiñones and Francisco J. Cazorla Timing Effects of DDR Memory Systems in Hard Real-Time Multicore. In ACM Transactions on Embedded Computing Systems.,Volume 12 Issue 1s. March 2013.
ACM TECS			Francisco J. Cazorla, Eduardo Quiñones, Tullio Vardanega, Liliana Cucu, Benoit Triquet, Guillem Bernat, Emery Berger, Jaume Abella, Franck Wartel, Michael Houston, Luca Santinelli, Leonidas Kosmidis, Code Lo, Dorin Maxim. PROARTIS: Probabilistically Analysable Real-Time Systems. In ACM Transactions on Embedded Computing Systems. Special issue on Probabilistic Computing,Volume 12 Issue 2sX, 2013.
ACM TECS			Marco Paolieri, Jorg Mische, Stefan Metzlaff, Mike Gerdes, Eduardo Quiñones, Sascha Uhrig, Theo Ungerer, Francisco J. Cazorla. A Hard Real-Time Capable Multi-Core SMT Processor. In ACM Transactions on Embedded Computing Systems. ,Volume 12 Issue 3, March 2013.
ACM TACO			Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Mateo Valero. Fair CPU Time Accounting in CMP+SMT Processors. In ACM Transactions on Architecture and Code Optimization (TACO). Presented at International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Berlin, Germany, January 2013.

2012

Conferences

MICRO			Petar Radojkovic, Paul M. Carpenter, Miquel Moreto, Alex Ramirez and Francisco J. Cazorla Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem In International Symposium on Microarchitecture (MICRO), December 2012 (MICRO). Vancouver, Canada. December
IISWC			Stelios Manousopoulos, Miquel Moreto, Roberto Gioiosa, Nectarios Koziris and Francisco J. Cazorla Characterizing Thread Placement in the IBM POWER7 Processor In IEEE International Symposium on Workload Characterization. San Diego, CA, USA, November.
EMSOFT			Mikel Fernandez, Roberto Gioiosa, Eduardo Quiñones, Luca Fossati, Marco Zulianello and Francisco J. Cazorla Assessing the suitability of the NGMP multi-core processor in the Space domain In International Conference on Embedded Software (EMSOFT). Tampere, Finland, October.
PACT			Victor Jimenez, R. Gioiosa, Francisco J. Cazorla, Alper Buyuktosunoglu, Pradip Bose, Frank P. OConnell Making Data Prefetch Smarter: Adaptive Prefetching on POWER7 Best Paper Award Nominee. In International Conference on Parallel Architectures and Compilation Techniques (PACT). Minneapolis, US, September.
ECRTS			Liliana Cucu-Grosjean, Luca Santinelli, Michael Houston, Code Lo, Tullio Vardanega, Leonidas Kosmidis, Jaume Abella, Enrico Mezzeti, Eduardo Quiñones, Francisco J. Cazorla Measurement-Based Probabilistic Timing Analysis for Multi-path Programs In Euromicro Conference on Real-Time Systems (ECRTS). Pisa, Italy, July.
ASPLOS			Petar Radojkovic, Vladimir Cakarevic, Miquel Moreto, Javier Verdu, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. Optimal Task Assignment in Multithreaded Processors: A Statistical Approach. In Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems. London, UK, March.
HiPEAC			Petar Radojkovic, Sylvain Girbal, Arnaud Grasset, Eduardo Quiñones, Sami Yehia, Francisco J. Cazorla. On the Evaluation of the Impact of Shared Resources in Multithreaded COTS Processors in Time-Critical Environments. In 7th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2012). January 23-25 2015. Paris, France.

Journals

IEEE ToC			Alessandro Morari, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose and Mateo Valero SMT Malleability in IBM POWER5 and POWER6 Processors. In IEEE Transaction on Computers, Volume 62 Issue 4, 2012.
IEEE ToC			C. Luque, M. Moreto, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu and M. Valero. CPU Accounting for Multicore Processors. In IEEE Transaction on Computers, Volume 61 Issue 2, February 2012.

2011

Conferences

IOLTS			Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero. RVC-Based Time-Predictable Faulty Caches for Safety-Critical Systems. In 17th International On-Line Testing Symposium (IOLTS). July 13-15 2011 . Athens , Greece.
IOLTS			Jaume Abella, Francisco J. Cazorla, Eduardo Quiñones, Dimitris Gizopoulos, Arnaud Grasset, Sami Yehia, Phillipe Bonnot, Riccardo Mariani, Guillem Bernat. Towards Improved Survivability in Safety-Critical Systems (invited paper). In 17th International On-Line Testing Symposium (IOLTS). July 13-15 2011 . Athens , Greece.
IPDPS			Alessandro Morari, Roberto Gioiosa, Robert Wisniewski, Francisco J. Cazorla, Mateo Valero A Quantitative Analysis of OS Noise. In 25th IEEE International Parallel & Distributed Processing Symposium (IPDPS). May, 2011. Alaska, USA.
RTAS			Marco Paolieri, Eduardo Quiñones, Frandisco J. Cazorla, Robert I. Davis and Mateo Valero IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems In 17th IEEE Real-Time and Embedded Technology and Applications Symposium . April 2011. Chicago, IL, USA.
ISORC			Marco Paolieri, Eduardo Quiñones, Frandisco J. Cazorla1, Julian Wolf, Theo Ungerer, Zlatko Petrov A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-Threaded Hard Real-Time Tasks In 14th IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing. March, 2011. Newport Beach, CA, USA.
HiPEAC			Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches In 6th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2011). January, 2011. NHeraklion, Crete (Greece).

Journals

IEEE CAS			Victor Jimenez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu and Pradip Bose. Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper) In IEEE Journal of Emerging and Selected Topics in Circuits and Systems,Volume 1 Issue 3, September 2011.
IEEE Micro			V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, C. A. Buyuktosunoglu, P. Bose, M. Valero. A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications. In IEEE Micro,Volume 31 Issue 3, April 2011.

2010

Conferences

VLSI-SoC			V. Jimenez, R. Gioiosa, E. Kursun, F. Cazorla, C. Cher, A. Buyuktosunoglu, P. Bose, M. Valero. Trends and Techniques for Energy Efficient Architectures. Invited Paper. In International Conference on VLSI and System-on-Chip (VLSI-SoC). September 2010. Madrid, Spain.
PACT			V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, C. Cher, A. Buyuktosunoglu, P. Bose, M. Valero. Power and Thermal Characterization of POWER6 System. In International Conference on Parallel Architectures and Compilation Techniques (PACT). September 11-15, 2010. Vienna, Austria.
ACLD			V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, M. Valero. A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. In Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA. June 2010. Sain-Malo, France.
IFMT			K. Kedzierski, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, M. Valero. Power and Performance Aware Reconfigurable Cache for CMPs. In Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA. June 2010. Sain-Malo, France.
CF			Miquel Moreto, Francisco J. Cazorla, Rizos Sakellariou and Mateo Valero. Load Balancing Using Dynamic Cache Allocation. In ACM International Conference on Computing Frontiers (CF). May 2010. Bertinoro, Italy.
IPDPS			Kamil Kedzierski, Miquel Moreto, Francisco J. Cazorla and Mateo Valero. Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS) April 19-23, 2010. ATLANTA (Georgia) USA .
PPoPP			Petar Radojkovic, Vladimir Cakarevic, Javier Verdu, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems. In 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming January 2010, Bangalore, India.

Journals

IEEE-ToC			Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez, and Mateo Valero. On the Problem of Evaluating the Performance of Multiprogrammed Workloads. In IEEE Transactions on Computers,Volume 59 Issue 12, Dec 2010.
IEEE-MICRO			Theo Ungerer, Francisco J. Cazorla, Pascal Sainrat, Guillem Bernat, Zlatko Petrov, Christine Rochange, Eduardo Quiñones, Mike Gerdes, Marco Paolieri, Julian Wolf, Hugues Casse, Sascha Uhrig, Irakli Guliashvili, Michael Houston, Florian Kluge, Stefan Metzlaff, Jorg Mische. MERASA: Multicore Execution of Hard Real-Time Applications Supporting Analyzability. In IEEEmicro,Volume 30 Issue 5, Sep/Oct 2010.

2009

Conferences

MICRO			Vladimir Cakarevic, Petar Radojkovic, Javier Verdu, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. Characterizing the resource-sharing levels in the UltraSPARC T2 Processor. In 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). New York City, USA, December 12-16, 2009.
SBAC-PAD			Carmelo Acosta, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero. Thread to Core Assignment in SMT On-Chip Multiprocessors. In 21st Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Sao Paulo, Brazil, October 28-31, 2009.
RePP			Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla and Mateo Valero. Efficient Execution of Mixed Application Workloads in a Hard Real-Time. In Workshop on Reconciling Performance with Predictability (RePP) Oct. 15, 2009, during the ESWEEK, in Grenoble, France.
PACT			Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu and Mateo Valero. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. In International Symposium on Parallel Architectures and Compilation Techniques. Raleigh, North Carolina. September 12-16, 2009.
PACT (Poster)			Kamil Kedzierski, Miquel Moreto, Francisco J. Cazorla and Mateo Valero. pseudo-LRU based Cache Partitioning Algorithms . In International Symposium on Parallel Architectures and Compilation Techniques. Raleigh, North Carolina. September 12-16, 2009.
ISCA			Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla, Guillem Bernat and Mateo Valero. Hardware Support for WCET Analysis of Multicore Systems . In International Symposium on Computer Architecture. Austin, USA. June 20-24, 2009.
ECRTS			Eduardo Quiñones, Emery Berger, Guillem Bernat and Francisco J. Cazorla Using Randomized Caches in Probabilistic Real-Time Systems. In 21st Euromicro Conference on Real-Time Systems (ECRTS 09). July 1-3, 2009, Dublin, Ireland.

Journals

OSR 2009			Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Rizos Sakellariou and Mateo Valero. FlexDCP: a QoS framework for CMP architectures. In ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors. April 2009.
IEEE-CAL			Carlos Luque, Miquel Moreto, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, and Mateo Valero. CPU accounting in CMP Processors. In IEEE Computer Architecture Letters. Volume 9, Issue 2, 2009.
IEEE-ESL			Marco Paolieri, Eduardo Quiñones, Francisco J. Cazorla and Mateo Valero. An Analyzable Memory Controller for Hard Real-Time CMPs . In IEEE Embedded Systems Letters Volume 1, Issue 4

2008

Conferences

SBAC-PAD			Petar Radojkovic, Vladimir Cakarevic, Javier Verdu, Alex Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky and Malero Valero. Measuring Operating System Overhead on CMT Processors. In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil. October 29 - November 1, 2008.
SBAC-PAD			Jesus Alastruey, Francisco J. Cazorla, Teresa Monreal, Victor Vinals and Mateo Valero. Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. In 20th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campo Grande, Brazil. October 29 - November 1, 2008.
SC			Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose and Mateo Valero. A Dynamic Scheduler for Balancing HPC Applications. In International Conference for High Performance Computing, Networking, Storage and Analysis (SC). Austin, USA. November 15-21, 2008.
ICPP			Carmelo Acosta, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero. MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. In International Conference on Parallel Processing. Portland, Oregon, USA. Oregon, USA. September 2008.
ISCA			Miquel Pericas, Ruben Gonzalez, Francisco J. Cazorla, Adrian Cristal, Alex Veidenbaum, Daniel A. Jimenez and Mateo Valero. A two-level Load/Store Queue based on Execution Locality. In International Symposium on Computer Architecture. Beijing, China. June 21-25, 2008.
ISCA			Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu and Mateo Valero. Software-Controlled Priority Characterization of POWER5 Processor. In International Symposium on Computer Architecture. Beijing, China. June 21-25, 2008.
WIOSCA			Vladimir Cakarevic, Petar Radojkovic, Javier Verdu, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. Understanding the overhead of the spin-lock loop in CMT architectures. In Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA). Beijing, China. June 22, 2008.
CEC			P. A. Castillo, J. J. Merelo, M. Moreto, F. J. Cazorla, M. Valero, A. M. Mora, J. L. J. Laredo, and S.A. McKee. Evolutionary system for prediction and optimization of hardware architecture performance. In IEEE Congress on Evolutionary Computation (CEC). Hong Kong. June 2008.
HiPEAC			Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero. MLP-aware dynamic cache partitioning. In International Conference on High Performance Embedded Architectures & Compilers. Goterborg, Sweeden. January 27-29, 2008.
IPDPS			Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Julita Corbalan, Jesus Labarta and Mateo Valero. Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. In International Parallel & Distributed Processing Symposium (IPDPS). Miami, Florida, USA. April 14-18, 2008.
EVOHOT			P. A. Castillo, A. M. Mora, J. J. Merelo, J. L. J. Laredo, M. Moreto, F. J. Cazorla, M. Valero, and S.A. McKee. Architecture performance prediction using evolutionary artificial neural networks. In European Workshop on Hardware Optimization Techniques (EVOHot). Napoli, Italy. March 2008.

Journals

HiPEAC			Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero. Dynamic Cache Partitioning Based on the MLP on Cache Misses. In Transactions on HiPEAC. Volume 3, Issue 1. May 2008.
IEEE-MICRO			Kyle J. Nesbit, Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero, and James E. Smith Multicore Resource Management. In IEEEmicro,Volume Issue , May/June 2008.
ARCS			Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa and Mateo Valero. Scheduling Real-Time Systems With Explicit Resource Allocation Processors. In International Conference on Architecture of Computing Systems (ARCS). Dresden, Germany. February 25,2008. Lecture Notes in Computer Science. Volume 4934/2008

2007

Conferences

SPEC-WORKSHOP			Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez, and Mateo Valero. Measuring the Performance of Multithreaded Processors. In SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)), Austin, USA. January 2007. Schaeffer Award to the technical quality of the paper.
CMP-MSI			Carmelo Acosta, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero. Core to Memory Interconexion Implications for Forthcomming On-Chip Multiprocessors. In Workshop on Chip Multiprocessor Memory Systems and Interconnects (in conjunction with the 13th Annual International Conference on High-Performance Architecture Phoenix, USA. February 2007.
IC-SAMOS			Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero. Online Prediction of Applications Cache Utility. In IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS ), Samos, Greece. July 16-19, 2007.
IC-SAMOS			Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. On the Problem of Minimizing Workload Execution Time in SMT Processors. In IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS ), Samos, Greece. July 16-19, 2007.
PACT			Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliveiro J. Santana, Enrique Fernandez and Mateo Valero. FAME: FAirly MEasuring Multithreaded Architectures. In Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania. September 15-19, 2007.
PACT			Miquel Pericas, Ruben Gonzalez, Adrian Cristal, Francisco J. Cazorla, Daniel A. Jimenez and Mateo Valero. A Flexible Heterogeneous Multi-Core Architecture. In Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania. September 15-19, 2007.
PACT (Poster)			Miquel Moreto, Francisco J. Cazorla, Alex Ramirez,nd Mateo Valero. MLP-aware dynamic cache partitioning. In Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania. September 15-19, 2007.

Journals

IEEE-CAL			Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, and Mateo Valero. Explaining Dynamic Cache Partitioning Speed Ups. In IEEE Computer Architecture Letters. Volume 6, Issue 1, March 2007.

2006

Conferences

MOBS			Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez, and Mateo Valero. A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures In Workshop on Modeling, Benchmarking and Simulation (MoBS)2006. Held in conjunction with ISCA, Boston, USA. June 2006.

Journals

IEEE-TC			Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. Predictable Performance in SMT processors: Synergy Between the OS and SMTs. In IEEE Transaction on Computers. Volume 55, Issue 7, July 2006.

2005

Conferences

CASES

Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. Architectural Support for Real-Time Task Scheduling in SMT Processors. In proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005), San Francisco, USA. September 2005.

Journals

IEEE-MICRO			Adrian Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzi, Tanausu Ramirez, Miquel Pericas, and Mateo Valero Kilo-instruction Processors: Overcoming the memory wall. In IEEEmicro,Volume 25 Issue 3, May/June 2005.

2004

Conferences

MICRO			Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero. Dynamically Controlled Resource Allocation in SMT Processors . In the 37th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Portland. December 2004.
DSD			Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. Implicit vs. Explicit Resource Allocation in SMT Processors. In EUROMICRO Symposium on Digital System Design. Invited Paper. Rennes, France. September 2004.
EUSIPCO			Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. Enabling SMT for Real-Time Embedded Systems. In 12th European Signal Processing Conference (EUSIPCO). Vienna-Austria. September 2004.
WCED			Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero. Approaching a Smart Sharing of Resources in SMT Processors. In Workshop on Complexity-Effective Design (WCED). Held in conjunction with ISCA., Munich, Germany. June, 2004.
IPDPS			Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero. DCache Warn: an I-Fetch Policy To Increase SMT Efficiency . In International Parallel and Distributed Processing Symposium (IPDPS 2004), Santa Fe, New Mexico. April 2004.
ACM-CF			Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. Predictable Performance in SMT Processors. In ACM conference on Computing Frontiers (CF-2004), Ischia, Italy. April 2004.

Journals

IEEE-MICRO			Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. QoS for High-Performance SMT Processors in Embedded Systems. In IEEE Micro . Volume 24, Issue 4, July/August 2004
EURO-PAR			Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. Feasibility of QoS for SMT by Resource Allocation. In the 10th International Euro-Par Conference. Published in Lecture Notes in Computer Science (LNCS) Volume 3149/2004., Pisa, Italy. September 2004.
IJHPCN			Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. In the International Journal of High Performance Computing and Networking. Special issue on ISHPC-V. Interscience publishers. April 2004

2003

Conferences

ISHPC

Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero. Improving Memory Latency Aware Fetch Policies for SMT Processors. In International Symposium on High Performance Computing (ISHPC-V), Tokyo, October 2003. Published in Lecture Notes in Computer Science (LNCS) 2858. Best Student Paper Award.